Texas Instruments SimpleLink CC3220MOD Series Manual page 40

CC3220MOD, CC3220MODA
SWRS206E – MARCH 2017 – REVISED MAY 2021
Table 8-5 lists the timing parameters for the SPI slave.
ITEM NAME
(1)
F
(1)
T2 T
clk
(1)
D
(1)
T6 t
IS
(1)
T7 t
IH
(1)
T8 t
OD
(1)
T9 t
OH
(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.
8.14.5.2 I2S
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit
and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A
fractional divider is available for bit-clock generation.
8.14.5.2.1 I2S Transmit Mode
Figure 8-10 shows the timing diagram for the I2S transmit mode.
Table 8-6 lists the timing parameters for the I2S transmit mode.
ITEM NAME
(1)
T1 f
clk
LP (1)
T2 t
(1)
T3 t
HT
(1)
T4 t
OH
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.5.2.2 I2S Receive Mode
Figure 8-11 shows the timing diagram for the I2S receive mode.
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Table 8-5. SPI Slave Timing Parameters
DESCRIPTION
Clock frequency @ VBAT = 3.3 V
Clock frequency @ VBAT ≤ 2.3 V
Clock period
Duty cycle
RX data setup time
RX data hold time
TX data output delay
TX data hold time
T2
McACLKX
McAFSX
McAXR0/1
Figure 8-10. I2S Transmit Mode Timing Diagram
Table 8-6. I2S Transmit Mode Timing Parameters
DESCRIPTION
Clock frequency
Clock low period
Clock high period
TX data hold time
T2
McACLKX
McAFSX
McAXR0/1
Figure 8-11. I2S Receive Mode Timing Diagram
Product Folder Links:
T1 T3
T4 T4
T1 T3
T5 T4
CC3220MOD CC3220MODA
www.ti.com
MIN MAX
20
12
50
45% 55%
4
4
20
24
MIN MAX
9.216
1/2 fclk
1/2 fclk
22
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UNIT
MHz
ns
ns
ns
ns
ns
UNIT
MHz
ns
ns
ns