Texas Instruments SimpleLink CC3220MOD Series Manual page 21

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GENERAL PIN ATTRIBUTES
Select
Pkg. Pin
Use Wakeu
Pin Alias
Source
WLAN
31 RF_BG
analog
32 GND GND
WLAN
33 NC
analog
Config
34 SOP0
sense
Global
35 nRESET
reset
VBAT_ Global
36
RESET reset
Supply
37 VBAT1
input
38 GND GND
WLAN
39 NC
analog
Supply
40 VBAT2
input
WLAN
41 NC
analog
42 GPIO30 I/O
43 GND GND
Copyright © 2021 Texas Instruments Incorporated
Table 7-3. Pin Attributes and Pin Multiplexing (continued)
FUNCTION
Confi
Dig. Pin
as g. Muxed
Mux
Addl. With
Config.
p Analo JTAG
Reg.
g Mux
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
User GPIO_PA
config D_
not CONFIG_3
No No
requir 0
ed (0x4402
(8)
E118)
N/A N/A N/A N/A
Product Folder Links:
SWRS206E – MARCH 2017 – REVISED MAY 2021
Dig.
Pin
Mux
Signal
Confi Signal Name
Description
g.
Mode
Value
CC3220MOD
x:
N/A RF BG band N/A
CC3220MOD
Ax: NC
N/A GND GND
NC Reserved
Sense-on-
N/A SOP0
power 0
Master chip
N/A nRESET reset. Active
low.
VBAT to
VBAT_RESE
N/A nRESET
T
pullup resistor
Analog
DC/DC input
(connected to
N/A VBAT1
chip input
supply
[VBAT])
N/A GND GND
N/A NC Reserved
Analog input
N/A VBAT2
supply VBAT
N/A NC Reserved
0 GPIO30 GPIO
UART0 TX
9 UART0_TX
data
I2S audio port
2 McACLK
clock
I2S audio port
3 McAFSX
frame sync
Timer capture
4 GT_CCP05
port
General SPI
7 GSPI_MISO
MISO
N/A GND GND
CC3220MOD CC3220MODA
CC3220MOD, CC3220MODA
PAD STATES
Signa
l LPD nRESET =
(2)
Hib
(1)
Direct S 0
ion
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
N/A N/A N/A N/A
Hi-Z,
I/O Pull,
Drive
O 1
Hi-Z,
O Pull,
Drive
Hi-Z,
Pull, Hi-Z
Hi-Z,
Drive
O Pull,
Drive
Hi-Z,
I Pull,
Drive
Hi-Z,
I/O Pull,
Drive
N/A N/A N/A N/A
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