Texas Instruments SimpleLink CC3220MOD Series Manual page 39

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Figure 8-8 shows the timing diagram for the SPI master.
CLK
MISO
MOSI
Table 8-4 lists the timing parameters for the SPI master.
ITEM NAME
(1)
F
(1)
T2 T
clk
(1)
D
(1)
T6 t
IS
(1)
T7 t
IH
(1)
T8 t
OD
(1)
T9 t
OH
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.5.1.2 SPI Slave
Figure 8-9 shows the timing diagram for the SPI slave.
CLK
MISO
MOSI
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T2
Figure 8-8. SPI Master Timing Diagram
Table 8-4. SPI Master Timing Parameters
DESCRIPTION
Clock frequency
Clock period
Duty cycle
RX data setup time
RX data hold time
TX data output delay
TX data hold time
T2
Figure 8-9. SPI Slave Timing Diagram
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T6 T7
T8
T6 T7
T8
CC3220MOD CC3220MODA
CC3220MOD, CC3220MODA
T9
MIN MAX UNIT
20 MHz
50 ns
45% 55%
1 ns
2 ns
8.5 ns
8 ns
T9
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