Figure 49. Usb_Otg_Fs Port Schematic Diagram - ST STM32L476G-EVAL User Manual

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Figure 49. USB_OTG_FS port schematic diagram

U1
2
GND FAULT
5
JP19 +5V IN
PC6 4
USBOTG_PPWR EN
Header 2X1 STMPS2151STR
R21
10K
PB13
USBOTG_PRDY
PA9
USBOTG_VBUS
PA11 R3 0
USBOTG_DM
PA12 R4 0
USBOTG_DP
PA10 R5 0
USBOTG_ID
D1
B3
Vbus ID
C3
D+out D+in
D3
D-out D-in
A2
Dz Pd1
B2
Pup Pd2
GND
EMIF02-USB03F2
USB Full Speed operating range voltage: 3.0V<VDDUSB<3.6V
PB12
USBOTG_OVRCR
+3V3 U5V
R9 R2
620 0
R8 LD6
47K
Red
3
1 1
OUT
2
C15 3
4
5
4.7uF
6
7
8
9
10
A3
C1
D1
B1
C2
D2
R1
1
47K
R261
22K
Title:
Project:
Size:
Date:
CN1
VBUS
DM
DP
ID
GND
Shield
Shield
Shield
Shield
EXP
475900001
+3V3
R6
330
LD5 VBUS OK
Green
T1
9013-SOT23
transistor pins numbers follow
SOT23 JEDEC standard,
USB_OTG_FS
STM32L476G-EVAL
A4 Reference: MB1144 Revision: B-02
6/24/2015 Sheet: 18 of 25