STM32L1xxx product families and describes the minimum hardware resources required to develop an STM32L1xxx application. Detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes. June 2011 Doc ID 17496 Rev 5 1/30 www.st.com...
Power supplies AN3216 Power supplies Introduction The device requires a 2.0 V to 3.6 V operating voltage supply (V ), to be fully functional at full speed. This maximum frequency is only achieved when the digital power voltage V CORE is equal to 1.8 V (product voltage range 1).
AN3216 Power supplies 2.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC and the DAC have an independent power supply that can be filtered separately, and shielded from noise on the PCB. ● The ADC voltage supply input is available on a separate V ●...
Power supplies AN3216 2.1.2 Independent LCD supply The V pin is provided to control the contrast of the glass LCD. This pin can be used in two ways: ● It can receive, from an external circuitry, the desired maximum voltage that is provided on the segment and common lines to the glass LCD by the microcontroller.
AN3216 Power supplies Power supply schemes The circuit is powered by a stabilized power supply, V ● The V pins must be connected to V with external decoupling capacitors; one single Tantalum or Ceramic capacitor (minimum 4.7 µF typical 10 µF) for the package + one 100 nF Ceramic capacitor for each V pin).
Power supplies AN3216 Figure 3. Power supply supervisors D DA 100 mV hysteresis 100 mV hysteresis IT enabled PVD output BOR reset (NRST) BOR/PDR reset (NRST) POR/PDR reset (NRST) (Note 1) BOR always active (Note 2) BOR disabled by option byte (Note 3) POR/PDR (BOR not available) (Note 4)
AN3216 Power supplies 2.3.1 Power-on reset (POR)/power-down reset (PDR), brownout reset (BOR) The monitoring voltage begins at 0.7 V. During power-on, for devices operating between 1.8 and 3.6 V, the BOR keeps the device under reset until the supply voltages (V and V ) come close to the lowest acceptable DDIO...
Power supplies AN3216 Figure 5. PVD thresholds 100 mV PVD threshold hysteresis PVD output 2.3.3 Brownout reset (BOR) During power on, the brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified V threshold. For devices operating from 1.65 to 3.6 V, the BOR option is not available and the power supply is monitored by the POR/PDR.
AN3216 Power supplies 2.3.4 System reset A system reset sets all registers to their reset values except for the RTC, backup registers and RCC control/status register, RCC_CSR. A system reset is generated when one of the following events occurs: A low level on the NRST pin (external reset) Window watchdog end-of-count condition (WWDG reset) Independent watchdog end-of-count condition (IWDG reset) A reset bit set by software (SWreset)
Clocks AN3216 Clocks Four different clock sources can be used to drive the system clock (SYSCLK). They are: ● HSI ((high-speed internal) oscillator clock ● HSE (high-speed external) oscillator clock ● PLL clock ● MSI (multispeed internal) oscillator clock The MSI is used as a system clock source after startup from reset, wake-up from Stop or Standby low power modes.
AN3216 Clocks HSE OSC clock The high-speed external clock signal (HSE) can be generated from two possible clock sources: ● HSE user external clock (see Figure ● HSE external crystal/ceramic resonator (see Figure Figure 7. External clock Figure 8. Crystal/ceramic resonators Hardware configuration OSC_IN OSC_OUT...
5 to 6 R (resonator series resistance). To fine tune the R value refer to AN2867 (Oscillator design guide for ST microcontrollers). 3.3.1 External source (LSE bypass) In this mode, an external clock source must be provided. It must have a frequency of 32.768 kHz.
AN3216 Clocks Clock security system (CSS) The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (clock security system interrupt, CSSI), allowing the MCU to perform rescue operations.
Boot configuration AN3216 Boot configuration Boot mode selection In the STM32L1xxx, three different boot modes can be selected by means of the BOOT[1:0] pins as shown in Table Table 1. Boot modes BOOT mode selection pins Boot mode Aliasing BOOT1 BOOT0 Main Flash memory is selected as boot Main Flash memory...
The embedded boot loader is used to reprogram the Flash memory through one of the following interfaces: USART1 or USART2. This program is located in the system memory and is programmed by ST during production (see the STM32L Flash programming manual for further details).
Figure 12 shows the connection of the host to a development board. The evaluation board (STM32L152-EVAL) embeds the debug tools (ST-LINK) so it can be directly connected to the PC through an USB cable. Figure 12. Host-to-board connection SWJ debug port (serial wire and JTAG) The STM32L1xxx core integrates the serial wire/JTAG debug port (SWJ-DP).
AN3216 Debug management 5.3.1 SWJ debug port pins Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose I/Os (GPIOs). These pins, shown in Table 2, are available on all packages. Table 2. Debug port pin assignment JTAG debug port SW debug port SWJ-DP pin name...
Debug management AN3216 5.3.3 Internal pull-up and pull-down resistors on JTAG pins The JTAG input pins must not be floating since they are directly connected to flip-flops which control the debug mode features. Special care must be taken with the SWCLK/TCK pin that is directly connected to the clock of some of these flip-flops.
AN3216 Recommendations Recommendations Printed circuit board For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to ground (V ) and another dedicated to the V supply. This provides good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board.
Recommendations AN3216 Figure 14. Typical layout for V pair Via to V Via to V Cap. STM32L1xxx Other signals When designing an application, the EMC performance can be improved by closely studying the following: ● Signals for which a temporary disturbance affects the running process permanently (which is the case for interrupts and handshaking strobe signals but, not the case for LED commands).
AN3216 Reference design Reference design Description The reference design shown in Figure 15, is based on the STM32L152VB(T6) This reference design can be tailored to any STM32L1xxx device with a different package, using the pin correspondence given in Table 6: Reference connection for all packages.
AN3216 Revision history Revision history Table 7. Document revision history Date Revision Changes 28-Jun-2010 Initial release Updated the following sections: Section 2.1: Introduction, Section 2.1.1: Independent A/D converter supply and reference voltage, Section 2.1.2: Independent LCD supply, Section 2.3.1: Power-on reset (POR)/power-down reset (PDR), brownout reset (BOR), and Section 2.3.4: System reset.
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