SWITCHING CHARACTERISTICS - CONTROL PORT - I
25 °C; VA+ = 5V, VD+ = 3/5V, ±10%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
2
Notes: 11. I
C is a registered trademark of Philips Semiconductors.
12. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
Stop
SDA
t buf
SCL
DS477PP1
Parameter
Start
t high
t hdst
t
t
low
hdd
Figure 4. I
Symbol
f
scl
t
buf
t
hdst
t
low
t
high
t
sust
(Note 12)
t
hdd
t
sud
t
r
t
f
t
susp
Repeated
Start
t
hdst
t sud
t sust
2
C Mode timing
CS8427
2
®
C
MODE
(Note 11, T
= 20pF)
L
Min
Typ
Max
-
-
100
4.7
-
-
4.0
-
-
4.7
-
-
4.0
-
-
4.7
-
-
0
-
-
250
-
-
-
-
25
-
-
25
4.7
-
-
Stop
t f
t susp
t r
=
A
Units
kHz
µ s
µ s
µ s
µ s
µ s
µ s
ns
ns
ns
µ s
9
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