Aes3 Transmitter And Receiver; Aes3 Receiver; Pll, Jitter Attenuation, Varispeed; Omck System Clock Mode - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

Figure 12 shows the entire data path clocked via the
PLL generated recovered clock. Figure 13 illus-
trates a standard AES3 receiver function. Figure 14
shows a standard AES3 transmitter function.

4.1 AES3 Transmitter and Receiver

The CS8427 includes an AES3 digital audio re-
ceiver and an AES3 digital audio transmitter. A
comprehensive buffering
read/write access to the channel status and user da-
ta. This buffering scheme is described in the Ap-
pendix: Channel Status and User Data Buffer
Management.

4.2 AES3 Receiver

The AES3 receiver accepts and decodes audio and
digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
The receiver consists of a differential input stage,
accessed via pins RXP and RXN, a PLL based
clock recovery circuit, and a decoder which sepa-
rates the audio data from the channel status and
user data.
External components are used to terminate and iso-
late the incoming data cables from the CS8427.
These components are detailed in the Appendix
"External AES/SPDIF/IEC60958 Transmitter and
Receiver Components".
4.2.1

PLL, Jitter Attenuation, Varispeed

An on-chip Phase Locked Loop (PLL) is used to re-
cover the clock from the incoming data stream. In
some applications, low jitter in the recovered clock,
presented on the RMCK pin, is important. For this
reason, the PLL has been designed to have good jit-
ter attenuation characteristics, shown in Figures 6
& 7. In addition, the PLL has been designed to only
use the preambles of the AES3 stream to provide
lock update information to the PLL. This results in
the PLL being immune to data dependent jitter ef-
fects, since the AES3 preambles do not vary with
the data. The PLL has the ability to lock onto a
12
scheme provides
wide range of input sample rates with no external
component changes. If the sample rate of the input
subsequently changes, for example in a varispeed
application, the PLL will only track up to ±12.5%
from the nominal center sample rate. The nominal
center sample rate is the sample rate that the PLL
first locks onto upon application of an AES3 data
stream or after enabling the CS8427 clocks by set-
ting the RUN control bit. If the 12.5% sample rate
limit is exceeded, the PLL will return to its wide
lock range mode and re-acquire a new nominal cen-
ter sample rate.
4.2.2

OMCK System Clock Mode

A special clock switching mode is available that al-
lows the clock that is input through the OMCK pin
to be output through the RMCK pin. This feature
is controlled by the SWCLK bit in register 1 of the
control registers. When the PLL loses lock, the fre-
quency of the VCO drops to 300 kHz. The clock
switching mode allows the clock input through
OMCK to be used as a clock in the system without
any disruption when the PLL loses lock, for exam-
ple, when the input is removed from the receiver.
When SWCLK is enabled and this mode is imple-
mented, RMCK is an output and is not bi-direction-
al. Please note that internal circuitry associated
with RMCK is not driven by OMCK.
4.2.3

PLL External Components

The PLL behavior is affected by the external filter
component values. Figure 5 shows the recommend-
ed configuration of the two capacitors and one re-
sistor required. There are two sets of component
values recommended, depending on whether the
AES3 receiver or ILRCK is used and the respective
sample rate used in the application, see Tables 1 &
2. Lock times are calculated as worst case for an Fsi
transition of 96kHz. The application note, AN159:
"PLL Filter Optimization for the CS8415A,
CS8420, and CS8427" provides further resources
for the PLL.
CS8427
DS477PP1