Appendix B: Channel Status And User Data Buffer Management; Aes3 Channel Status(C) Bit Management; Manually Accessing The E Buffer; Figure 29. Channel Status Data Buffer Structure - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

14. APPENDIX B: CHANNEL STATUS
AND USER DATA BUFFER
MANAGEMENT
The CS8427 has a comprehensive channel status
(C) and user (U) data buffering scheme, which al-
lows automatic management of channel status
blocks and user data. Alternatively, sufficient con-
trol and access is provided to allow the user to com-
pletely manage the C and U data via the control
port.
14.1 AES3 Channel Status(C) Bit
Management
The CS8427 contains sufficient RAM to store a full
block of C data for both A and B channels (192x2
= 384 bits), and also 384 bits of U information. The
user may read from or write to these RAMs via the
control port.
The CS8427 manages the flow of channel status
data at the block level, meaning that entire blocks
of channel status information are buffered at the in-
put, synchronized to the output timebase, and then
transmitted. The buffering scheme involves a cas-
cade of 3 block-sized buffers, named D,E and F, as
shown in Figure 29. The MSB of each byte repre-
sents the first bit in the serial C data stream. For
example, the MSB of byte 0 (which is at control
From
AES3
Receiver
DS477PP1
A
8-bits
D
Received
Data
Buffer
Control Port

Figure 29. Channel Status Data Buffer Structure

port address 32) is the consumer/professional bit
for channel status block A.
The first buffer, D, accepts incoming C data from
the AES receiver. The 2nd buffer, E, accepts entire
blocks of data from the D buffer. The E buffer is
also accessible from the control port, allowing read
and writing of the C data. The 3rd buffer (F) is used
as the source of C data for the AES3 transmitter.
The F buffer accepts block transfers from the E
buffer.

14.1.1 Manually accessing the E buffer

The user can monitor the data being transferred by
reading the E buffer, which is mapped into the reg-
ister space of the CS8427, via the control port. The
user can modify the data to be transmitted by writ-
ing to the E buffer.
The user can configure the interrupt enable register
to cause interrupts to occur whenever "D to E" or
"E to F" buffer transfers occur. This allows deter-
mination of the allowable time periods to interact
with the E buffer.
Also provided are "D to E" and "E to F" inhibit
bits. The associated buffer transfer is disabled
whenever the user sets these bits. These may be
used whenever "long" control port interactions are
occurring. They can also be used to align the be-
B
8-bits
E F
24
Transmit
words
Data
Buffer
CS8427
To
AES3
Transmitter
51