General Description; Data I/O Flow And Clocking Options - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

3. GENERAL DESCRIPTION

The CS8427 is an AES3 transceiver intended to be
used in digital audio systems. Such systems include
digital mixing consoles, effects processors, tape re-
corders and computer multimedia systems.
On the input side of the CS8427, AES3 or a 3-wire
serial format can be chosen. The output side pro-
duces both AES3 and a 3-wire serial format. An
2
I C/SPI compatible microcontroller interface al-
lows full block processing of channel status and
user data via block reads from the incoming AES3
data stream and block writes to the outgoing AES3
data stream. The user can also access information
decoded from the input AES3 data stream, such as
the presence of non-audio data and preemphasis, as
well as control the various modes of the device. For
users who prefer not to use a micro-controller, a
hardware mode has been provided, documented to-
wards the end of this data sheet.
When used for AES3 I/O applications, the CS8427
can automatically transceive user data that con-
forms to the IEC60958 recommended format. The
CS8427 also allows access to the relevant bits in
the AES3 data stream to comply with the serial
copy management system (SCMS).
The diagram on the cover of this data sheet shows
the main functional blocks of the CS8427. Figure 5
shows the supply and external connections to the
device.
Familiarity with the AES3 and IEC60958 specifi-
cations are assumed throughout this document. The
Application Note: "Overview of Digital Audio In-
terface Data Structures" contains a tutorial on digi-
tal audio specifications.
Understanding and Implementation of the SCMS
Serial Copy Management System for Digital Audio
Transmission", by Clif Sanchez, is an excellent tu-
torial on SCMS. It may be obtained from Cirrus
Logic, or from the AES.
DS477PP1
The paper "An
To guarantee system compliance, the proper stan-
dards documents should be obtained. The latest
AES3 standard should be obtained from the Audio
Engineering Society or ANSI, the latest IEC60958
standard from the International Electrotechnical
Commission and the latest EIAJ CP-1201 standard
from the Japanese Electronics Bureau.
4. DATA I/O FLOW AND CLOCKING
OPTIONS
The CS8427 can be configured for several connec-
tivity alternatives, called data flows. Figure 10
shows the data flow switching, along with the con-
trol register bits which control the switches; this
drawing only shows the audio data paths for sim-
plicity. Users should note that not all the possible
data flow switch setting combinations are valid, be-
cause of the clock distribution architecture.
The AESBP switch allows a TTL level, already bi-
phase mark encoded, data stream connected to
RXP to be routed to the TXP and TXN pin drivers.
The TXOFF switch causes the TXP and TXN out-
puts to be driven to ground.
There are two possible clock sources. The first is
known as the recovered clock, is the output of a
PLL, and is connected to the RMCK pin. The input
to the PLL can be either the incoming AES3 data
stream or the ILRCK word rate clock from the se-
rial audio input port. The second clock is input via
the OMCK pin and would normally be a crystal de-
rived stable clock. The Clock Source Control Reg-
ister bits determine which clock is used to operate
the CS8427.
By studying the following drawings and appropri-
ately setting the Data Flow Control and Clock
Source Control register bits, the CS8427 can be
configured to fit a variety of customer require-
ments. Please note that applications implementing
both the Serial Audio Output Port and the AES3
Transmitter must operate at the same sample rate
because they are both controlled by the same clock
source.
CS8427
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