Receiver Error Mask (17); Channel Status Data Buffer Control (18) - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

7.15 Receiver Error Mask (17)

7 6
0 QCRCM
The bits in this register serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set
to 1, the error is considered unmasked, meaning that its occurrence will appear in the receiver error register, will
affect the RERR pin, will affect the RERR interrupt, and will affect the current audio sample according to the status
of the HOLD bit. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not appear
in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the
current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not affect the current
audio sample even when unmasked. This register defaults to 00h.

7.16 Channel Status Data Buffer Control (18)

7 6
0 0
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = '0'
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
CBMR - Control for the first 5 bytes of channel status "E" buffer
Default = '0'
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data
DETCI - D to E C-data buffer transfer inhibit bit.
Default = '0'
0 - Allow C-data D to E buffer transfers
1 - Inhibit C-data D to E buffer transfers
EFTCI - E to F C-data buffer transfer inhibit bit.
Default = '0'
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
CAM - C-data buffer control port access mode bit
Default = '0'
0 - One byte mode
1 - Two byte mode
CHS - Channel select bit
Default = '0'
0 - Channel A information is displayed at the EMPH pin and in the receiver channel
status register. Channel A information is output during control port reads when
CAM is set to 0 (One Byte Mode)
1 - Channel B information is displayed at EMPH pin and in the receiver channel
status register. Channel B information is output during control port reads when
CAM is set to 0 (One Byte Mode)
36
5 4
CCRCM UNLOCKM
5 4
BSEL CBMR
3 2
VM CONFM
3 2
DETCI EFTCI
CS8427
1 0
BIPM PARM
1 0
CAM CHS
DS477PP1