Figure 15. Aes3 Receiver Timing For U Pin Output Data; Figure 16. Aes3 Transmitter Timing For C, U And V Pin Input Data - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

VLRCK
U
Output
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the U timing.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If the serial audio output port is in master mode, VLRCK = OLRCK.
If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
U transitions are aligned within 1% of VLRCK period to VLRCK edges
TCBL
in or out
VLRCK
C, U, V
Input
TCBL
in or out
VLRCK
U
Input
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CUV timing.
VLRCK duty cycle is 50%.
In stereo mode, VLRCK = AES3 frame rate. In mono mode, VLRCK = 2*AES3 frame rate
If the serial audio output port is in master mode, and TCBL is an output,
then VLRCK = OLRCK.
If the serial audio input port is in master mode, and TCBL is an input, then VLRCK = ILRCK.
Otherwise, VLRCK needs to be externally created, if required
20
±

Figure 15. AES3 Receiver Timing for U pin output data

AES3 Transmitter in Stereo Mode
CUV
Tsetup Thold
AES3 Transmitter in Mono Mode

Figure 16. AES3 Transmitter Timing for C, U and V pin input data

CUV
Tsetup = >7.5% AES3 frame time
Thold = 0
U
Tsetup Thold Tsetup = >15% AES3 frame time
Thold = 0
CS8427
CUV CUV
U
DS477PP1