Cirrus Logic Crystal CS8427 Series Preliminary Product Information page 3

7.4 Clock Source Control (4) .................................................................................................. 29
7.5 Serial Audio Input Port Data Format (5) ........................................................................... 30
7.6 Serial Audio Output Port Data Format (6) ........................................................................ 31
7.7 Interrupt 1 Status (7) (Read Only) .................................................................................... 32
7.8 Interrupt 2 Status (8) (Read Only) .................................................................................... 32
7.9 Interrupt 1 Mask (9) .......................................................................................................... 33
7.10 Interrupt 1 Mode MSB (10) & Interrupt 1 Mode LSB (11) ............................................... 33
7.11 Interrupt 2 Mask (12) ...................................................................................................... 33
7.12 Interrupt 2 Mode MSB (13) & Interrupt 2 Mode LSB (14) ............................................... 33
7.13 Receiver Channel Status (15) (Read Only) .................................................................... 34
7.14 Receiver Error (16) (Read Only)..................................................................................... 35
7.15 Receiver Error Mask (17) ............................................................................................... 36
7.16 Channel Status Data Buffer Control (18) ........................................................................ 36
7.17 User Data Buffer Control (19) ......................................................................................... 37
7.18 Q-Channel Subcode Bytes 0 to 9 (20 - 29) (Read Only) ................................................ 38
7.19 OMCK/RMCK Ratio (30) (Read Only) ............................................................................ 38
7.20 C-bit or U-bit Data Buffer (32 - 55) ................................................................................. 38
7.21 CS8427 I.D. and Version Register (127) (Read Only).................................................... 38
8. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 39
9. HARDWARE MODE DESCRIPTION ..................................................................................... 41
9.1 Serial Audio Port Formats ............................................................................................... 41
10. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 43
11. APPLICATIONS ................................................................................................................... 45
11.1 Reset, Power Down and Start-up .................................................................................. 45
11.2 ID Code and Revision Code .......................................................................................... 45
11.3 Power Supply, Grounding, and PCB layout ................................................................... 45
11.4 Synchronization of Multiple CS8427s ............................................................................ 46
12. PACKAGE DIMENSIONS .................................................................................................... 47
13. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958
TRANSMITTER AND RECEIVER COMPONENTS ............................................................. 49
13.1 AES3 Transmitter External Components ....................................................................... 49
13.2 AES3 Receiver External Components ........................................................................... 50
13.3 Isolating Transformer Requirements ............................................................................. 50
14. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 51
14.1 AES3 Channel Status(C) Bit Management .................................................................... 51
14.1.1 Manually accessing the E buffer ....................................................................... 51
14.1.2 Reserving the first 5 bytes in the E buffer ......................................................... 52
14.1.3 Serial Copy Management System (SCMS) ....................................................... 52
14.1.4 Channel Status Data E Buffer Access .............................................................. 53
14.2 AES3 User (U) Bit Management .................................................................................... 53
14.2.1 Mode 1: Transmit All Zeros ............................................................................... 53
14.2.2 Mode 2: Block Mode ......................................................................................... 53
DS477PP1
CS8427
3