Switching Characteristics - Serial Audio Ports; Figure 1. Audio Port Master Mode Timing; Figure 2. Audio Port Slave Mode And Data Input Timing - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

VD+ = 3/5V, ±10%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C
OSCLK Active Edge to SDOUT Output Valid
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
O/RMCK to I/OSCLK active edge delay
O/RMCK to I/OLRCK delay
I/OSCLK and I/OLRCK Duty Cycle
Slave Mode
I/OSCLK Period
I/OSCLK Input Low Width
I/OSCLK Input High Width
I/OSCLK Active Edge to I/OLRCK Edge
I/OLRCK Edge Setup Before I/OSCLK Active Edge
Notes: 4. The active edges of ISCLK and OSCLK are programmable.
5. The polarity of ILRCK and OLRCK is programmable.
6. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
7. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has
changed.
ISCLK
OSCLK
(output)
ILRCK
OLRCK
(output)
t smd
RMCK
OMCK
(input)

Figure 1. Audio Port Master Mode Timing

DS477PP1
Parameter
t
lmd
= 20pF)
L
Symbol
(Note 4) t
dpd
(Note 4) t
ds
(Note 4) t
dh
(Note 4) t
smd
(Note 5) t
lmd
t
sckw
t
sckl
t
sckh
(Note 4,5,6) t
lrckd
(Note t
lrcks
4,5,7)
ILRCK
OLRCK
(input)
t
lrckd
ISCLK
OSCLK
(input)
SDIN
SDOUT

Figure 2. Audio Port Slave Mode and Data Input Timing

(T = 25 °C; VA+ = 5V,
A
Min Typ Max
- - 20
20 - -
20 - -
0 - 10
0 - 10
- 50 -
36 - -
14 - -
14 - -
20 - -
20 - -
t t t
lrcks sckh
sckl
t
sckw
t t
t dpd
ds dh
CS8427
Units
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
7