Cirrus Logic CS42518-DQ Manuals

Manuals and User Guides for Cirrus Logic CS42518-DQ. We have 1 Cirrus Logic CS42518-DQ manual available for free PDF download: Instructions Manual

Cirrus Logic CS42518-DQ Instructions Manual (87 pages)

Brand: Cirrus Logic | Category: Receiver | Size: 1 MB

Table of Contents
2
Characteristics and Specifications
6
Specified Operating Conditions
6
Absolute Maximum Ratings
6
Analog Input Characteristics
7
A/D Digital Filter Characteristics
8
Analog Output Characteristics
9
D/A Digital Filter Characteristics
10
Switching Characteristics
11
Figure 1. Serial Audio Port Master Mode Timing
11
Figure 2. Serial Audio Port Slave Mode Timing
11
Switching Characteristics - Control Port - I2C Format
12
Figure 3. Control Port Timing - I2C Format
12
Switching Characteristics - Control Port - Spi Format
13
Figure 4. Control Port Timing - SPI Format
13
DC Electrical Characteristics
14
Digital Interface Characteristics
14
Pin Descriptions
15
Typical Connection Diagrams
18
Figure 5. Typical Connection Diagram
18
Figure 6. Typical Connection Diagram with PLL
19
Applications
20
Overview
20
Analog Inputs
20
Line Level Inputs
20
Figure 7. Full-Scale Analog Input
20
High Pass Filter and DC Offset Calibration
21
Analog Outputs
21
Line Level Outputs and Filtering
21
Interpolation Filter
21
Figure 8. Full-Scale Output
21
Digital Volume and Mute Control
22
ATAPI Specification
22
Figure 9. ATAPI Block Diagram (X = Channel Pair 1, 2, 3, 4)
22
S/PDIF Receiver
23
8:2 S/PDIF Input Multiplexer
23
Error Reporting and Hold Function
23
Channel Status Data Handling
23
User Data Handling
23
Non-Audio Auto-Detection
23
Clock Generation
24
PLL and Jitter Attenuation
24
Figure 10. CS42518 Clock Generation
24
OMCK System Clock Mode
25
Master Mode
25
Slave Mode
25
Table 1. Common OMCK Clock Frequencies
25
Table 2. Common PLL Output Clock Frequencies
25
Table 3. Slave Mode Clock Ratios
25
Digital Interfaces
26
Serial Audio Interface Signals
26
Table 4. Serial Audio Port Channel Allocations
26
Serial Audio Interface Formats
28
Figure 11. I 2 S Serial Audio Formats
28
Figure 12. Left Justified Serial Audio Formats
29
Figure 13. Right Justified Serial Audio Formats
29
Figure 14. One Line Mode #1 Serial Audio Format
30
Figure 15. One Line Mode #2 Serial Audio Format
30
ADCIN1/ADCIN2 Serial Data Format
31
Figure 16. ADCIN1/ADCIN2 Serial Audio Format
31
One Line Mode(OLM) Configurations
32
OLM Config #1
32
Figure 17. OLM Configuration #1
32
OLM Config #2
33
Figure 18. OLM Configuration #2
33
OLM Config #3
34
Figure 19. OLM Configuration #3
34
OLM Config #4
35
Figure 20. OLM Configuration #4
35
OLM Config #5
36
Figure 21. OLM Configuration #5
36
Control Port Description and Timing
37
SPI Mode
37
Figure 22. Control Port Timing in SPI Mode
37
I2C Mode
38
Figure 23. Control Port Timing, I2C Write
38
Figure 24. Control Port Timing, I2C Read
38
Interrupts
39
Reset and Power-Up
39
Power Supply, Grounding, and PCB Layout
39
Register Quick Reference
41
Register Description
45
Memory Address Pointer (MAP)
45
Chip I.D. and Revision Register (Address 01H) (Read Only)
45
Power Control (Address 02H)
46
Functional Mode (Address 03H)
46
Table 5. DAC De-Emphasis
47
Interface Formats (Address 04H)
48
Table 6. Receiver De-Emphasis
48
Table 7. Digital Interface Formats
48
Table 8. ADC One-Line Mode
49
Table 9. DAC One-Line Mode
49
Misc Control (Address 05H)
50
Clock Control (Address 06H)
51
Table 10. RMCK Divider Settings
51
Table 11. OMCK Frequency Settings
52
Table 12. Master Clock Source Select
52
OMCK/PLL_CLK Ratio (Address 07H) (Read Only)
53
RVCR Status (Address 08H) (Read Only)
53
Table 13. AES Format Detection
53
Burst Preamble PC and PD Bytes (Addresses 09H - 0Ch)(Read Only)
54
Table 14. Receiver Clock Frequency Detection
54
Volume Transition Control (Address 0Dh)
55
Channel Mute (Address 0Eh)
57
Volume Control (Addresses 0Fh, 10H, 11H, 12H, 13H, 14H, 15H, 16H)
57
Channel Invert (Address 17H)
57
Table 15. Example Digital Volume Settings
57
Mixing Control Pair 1 (Channels A1 & B1)(Address 18H)
58
Mixing Control Pair 2 (Channels A2 & B2)(Address 19H)
58
Mixing Control Pair 3 (Channels A3 & B3)(Address 1Ah)
58
Mixing Control Pair 4 (Channels A4 & B4)(Address 1Bh)
58
Table 16. ATAPI Decode
59
ADC Left Channel Gain (Address 1Ch)
60
ADC Right Channel Gain (Address 1Dh)
60
Receiver Mode Control (Address 1Eh)
60
Table 17. Example ADC Input Gain Settings
60
Receiver Mode Control 2 (Address 1Fh)
61
Table 18. TXP Output Selection
61
Interrupt Status (Address 20H) (Read Only)
62
Table 19. Receiver Input Selection
62
Interrupt Mask (Address 21H)
63
Interrupt Mode MSB (Address 22H) Interrupt Mode LSB (Address 23H)
63
Channel Status Data Buffer Control (Address 24H)
64
Receiver Channel Status (Address 25H) (Read Only)
64
Receiver Errors (Address 26H) (Read Only)
65
Table 20. Auxiliary Data Width Selection
65
Receiver Errors Mask (Address 27H)
67
Mutec Pin Control (Address 28H)
67
Rxp/General Purpose Pin Control (Addresses 29H to 2Fh)
68
Q-Channel Subcode Bytes 0 to 9 (Addresses 30H to 39H) (Read Only)
69
C-Bit or U-Bit Data Buffer (Addresses 3Ah to 51H) (Read Only)
69
Parameter Definitions
70
References
71
Package Dimensions
72
Thermal Characteristics
72
Appendix A: External Filters
73
ADC Input Filter
73
DAC Output Filter
73
Figure 25. Recommended Analog Input Buffer
73
Figure 26. Recommended Analog Output Buffer
73
Appendix B: S/Pdif Receiver
74
Error Reporting and Hold Function
74
Channel Status Data Handling
74
Channel Status Data E Buffer Access
75
One Byte Mode
75
Two Byte Mode
75
Figure 27. Channel Status Data Buffer Structure
75
Serial Copy Management System (SCMS)
76
User (U) Data E Buffer Access
76
Non-Audio Auto-Detection
76
Format Detection
76
Appendix C: Pll Filter
77
Figure 28. PLL Block Diagram
77
External Filter Components
78
General
78
Jitter Attenuation
78
Figure 29. Jitter Attenuation Characteristics of PLL
78
Table 21. PLL External Component Values
78
Capacitor Selection
79
Circuit Board Layout
79
Figure 30. Recommended Layout Example
79
Appendix D: External Aes3/Spdif/Iec60958 Receiver Components
80
AES3 Receiver External Components
80
Figure 31. Consumer Input Circuit
80
Figure 32. S/PDIF MUX Input Circuit
80
Figure 33. TTL/CMOS Input Circuit
80
Appendix E: Adc Filter Plots
81
Figure 34. Single Speed Mode Stopband Rejection
81
Figure 35. Single Speed Mode Transition Band
81
Figure 36. Single Speed Mode Transition Band (Detail)
81
Figure 37. Single Speed Mode Passband Ripple
81
Figure 38. Double Speed Mode Stopband Rejection
81
Figure 39. Double Speed Mode Transition Band
81
Figure 40. Double Speed Mode Transition Band (Detail)
82
Figure 41. Double Speed Mode Passband Ripple
82
Figure 42. Quad Speed Mode Stopband Rejection
82
Figure 43. Quad Speed Mode Transition Band
82
Figure 44. Quad Speed Mode Transition Band (Detail)
82
Figure 45. Quad Speed Mode Passband Ripple
82
Appendix F: Dac Filter Plots
83
Figure 46. Single Speed (Fast) Stopband Rejection
83
Figure 47. Single Speed (Fast) Transition Band
83
Figure 48. Single Speed (Fast) Transition Band (Detail)
83
Figure 49. Single Speed (Fast) Passband Ripple
83
Figure 50. Single Speed (Slow) Stopband Rejection
83
Figure 51. Single Speed (Slow) Transition Band
83
Figure 52. Single Speed (Slow) Transition Band (Detail)
84
Figure 53. Single Speed (Slow) Passband Ripple
84
Figure 54. Double Speed (Fast) Stopband Rejection
84
Figure 55. Double Speed (Fast) Transition Band
84
Figure 56. Double Speed (Fast) Transition Band (Detail)
84
Figure 57. Double Speed (Fast) Passband Ripple
84
Figure 58. Double Speed (Slow) Stopband Rejection
85
Figure 59. Double Speed (Slow) Transition Band
85
Figure 60. Double Speed (Slow) Transition Band (Detail)
85
Figure 61. Double Speed (Slow) Passband Ripple
85
Figure 62. Quad Speed (Fast) Stopband Rejection
85
Figure 63. Quad Speed (Fast) Transition Band
85
Figure 64. Quad Speed (Fast) Transition Band (Detail)
86
Figure 65. Quad Speed (Fast) Passband Ripple
86
Figure 66. Quad Speed (Slow) Stopband Rejection
86
Figure 67. Quad Speed (Slow) Transition Band
86
Figure 68. Quad Speed (Slow) Transition Band (Detail)
86
Figure 69. Quad Speed (Slow) Passband Ripple
86
Table 22. Revision History
87

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