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CS2100-CP
Cirrus Logic CS2100-CP Manuals
Manuals and User Guides for Cirrus Logic CS2100-CP. We have
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Cirrus Logic CS2100-CP manual available for free PDF download: Manual
Cirrus Logic CS2100-CP Manual (33 pages)
Fractional-N Clock Multiplier
Brand:
Cirrus Logic
| Category:
Synthesizer
| Size: 1 MB
Table of Contents
Table of Contents
2
Pin Description
4
Typical Connection Diagram
5
Figure 1. Typical Connection Diagram
5
Characteristics and Specifications
6
Recommended Operating Conditions
6
Absolute Maximum Ratings
6
DC Electrical Characteristics
6
Ac Electrical Characteristics
7
Pll Performance Plots
8
Figure 2. CLK_IN Sinusoidal Jitter Tolerance
8
Figure 3. CLK_IN Sinusoidal Jitter Transfer
8
Figure 4. CLK_IN Random Jitter Rejection and Tolerance
8
Control Port Switching Characteristics- I²C Format
9
Figure 5. Control Port Timing - I²C Format
9
Control Port Switching Characteristics - Spi Format
10
Figure 6. Control Port Timing - SPI Format (Write Only)
10
Architecture Overview
11
Delta-Sigma Fractional-N Frequency Synthesizer
11
Hybrid Analog-Digital Phase Locked Loop
11
Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer
11
Figure 8. Hybrid Analog-Digital PLL
12
Applications
13
Timing Reference Clock Input
13
Internal Timing Reference Clock Divider
13
Figure 9. Internal Timing Reference Clock Divider
13
Figure 10. REF_CLK Frequency Vs. a Fixed CLK_OUT
13
Crystal Connections (XTI and XTO)
14
External Reference Clock (REF_CLK)
14
Frequency Reference Clock Input, CLK_IN
14
CLK_IN Skipping Mode
14
Figure 11. External Component Requirements for Crystal Circuit
14
Figure 12. CLK_IN Removed for > 2
15
Sysclk Cycles
15
Figure 13. CLK_IN Removed for < 2
15
Sysclk Cycles but > T CS
15
Adjusting the Minimum Loop Bandwidth for CLK_IN
16
Figure 14. CLK_IN Removed for < T CS
16
Output to Input Frequency Ratio Configuration
17
User Defined Ratio (RUD)
17
Figure 15. Low Bandwidth and New Clock Domain
17
Figure 16. High Bandwidth with CLK_IN Domain Re-Use
17
Ratio Modifier (R-Mod)
18
Table 1. Ratio Modifier
18
Effective Ratio (REFF)
19
Ratio Configuration Summary
19
Figure 17. Ratio Feature Summary
19
PLL Clock Output
20
Auxiliary Output
20
Figure 18. PLL Clock Output Options
20
Figure 19. Auxiliary Output Selection
20
Clock Output Stability Considerations
21
Output Switching
21
PLL Unlock Conditions
21
Required Power up Sequencing
21
Spi / I²C Control Port
21
SPI Control
22
I²C Control
22
Figure 20. Control Port Timing in SPI Mode
22
Figure 21. Control Port Timing, I²C Write
23
Figure 22. Control Port Timing, I²C Aborted Write + Read
23
Memory Address Pointer
24
Map Auto Increment
24
Register Quick Reference
24
Register Descriptions
25
Device I.D. and Revision (Address 01H)
25
Device Identification (Device[4:0]) - Read Only
25
Device Revision (Revision[2:0]) - Read Only
25
Device Control (Address 02H)
25
Unlock Indicator (Unlock) - Read Only
25
Auxiliary Output Disable (Auxoutdis)
25
PLL Clock Output Disable (Clkoutdis)
26
Device Configuration 1 (Address 03H)
26
R-Mod Selection (Rmodsel[2:0])
26
Auxiliary Output Source Selection (Auxoutsrc[1:0])
26
Enable Device Configuration Registers 1 (Endevcfg1)
27
Global Configuration (Address 05H)
27
Device Configuration Freeze (Freeze)
27
Enable Device Configuration Registers 2 (Endevcfg2)
27
Ratio (Address 06H - 09H)
27
Function Configuration 1 (Address 16H)
28
Clock Skip Enable (Clkskipen)
28
AUX PLL Lock Output Configuration (Auxlockcfg)
28
Reference Clock Input Divider (Refclkdiv[1:0])
28
Function Configuration 2 (Address 17H)
29
Enable PLL Clock Output on Unlock (Clkoutunl)
29
Low-Frequency Ratio Configuration (Lfratiocfg)
29
Function Configuration 3 (Address 1Eh)
29
Clock Input Bandwidth (Clkin_Bw[2:0])
29
Calculating the User Defined Ratio
30
High Resolution 12.20 Format
30
High Multiplication 20.12 Format
30
Table 2. Example 12.20 R-Values
30
Table 3. Example 20.12 R-Values
30
10.Package Dimensions
31
Thermal Characteristics
31
Ordering Information
32
References
32
12.Revision History
32
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