Interrupts; Figure 19. Control Port Timing In Spi Mode; Figure 20. Control Port Timing In I2C Mode - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

knowledge bit, ACK, which is output from the
CS8427 after each input byte is read. The ACK bit
is input to the CS8427 from the microcontroller af-
ter each transmitted byte. I
mark of Philips Semiconductors.

5.3 Interrupts

The CS8427 has a comprehensive interrupt capa-
bility. The INT output pin is intended to drive the
interrupt input pin on the host microcontroller. The
INT pin may be set to be active low, active high, or
active low with no active pull-up transistor. This
last mode is used for active low, wired-OR hook-
CS
C C L K
C H IP
ADDRESS
0010000
C D IN
High Impedance
C D O U T
MAP = Memory Address Pointer, 8 bits, MSB first
SDA
SCL
Start
Note 1: AD2 is derived from a resistor attached to the EMPH pin,
Note 2: If operation is a write, this byte contains the Memory Address Pointer, MAP
24
2
C is a registered trade-
M A P DATA
MSB
R/W
b y te 1

Figure 19. Control Port Timing in SPI Mode

Note 1
0010 AD2-0
R/W
AD1 and AD0 are determined by the state of the corresponding pins
Figure 20. Control Port Timing in I
ups with multiple peripherals connected to the mi-
crocontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in
the interrupt status register descriptions. Each
source may be masked off via mask registers. In ad-
dition, each source may be set to rising edge, fall-
ing edge, or level sensitive. Combined with the
option of level sensitive or edge sensitive modes
within the microcontroller, many different set-ups
are possible depending on the needs of the equip-
ment designer.
C H IP
A D D R E S S
0010000
LSB
b y te n
Note 2
ACK DATA7-0 ACK
2
C Mode
R/W
LSB MSB
MSB
DATA7-0
ACK
Stop
CS8427
LSB
DS477PP1