Control Port Register Bit Definitions; Control 1 (1) - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

7. CONTROL PORT REGISTER BIT DEFINITIONS

7.1 Control 1 (1)

7 6
SWCLK VSET
SWCLK - Controls output of OMCK on RMCK when PLL loses lock
Default = '0'
0 - RMCK default function
1 - OMCK output on RMCK pin
VSET - Transmitted V bit level
Default = '0'
0 - Indicates data is valid, linear PCM audio data
1 - Indicates data is invalid or not linear PCM audio data
MUTESAO - Mute control for the serial audio output port
Default = '0'
0 - Disabled
1 - Enabled
MUTEAES - Mute control for the AES transmitter output
Default = '0'
0 - Disabled
1 - Enabled
INT1:INT0 - Interrupt output pin (INT) control
Default = '00'
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull up resistor on the INT pin.
11 - Reserved
TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier
Default = '0'
0 - TCBL is an input
1 - TCBL is an output
26
5 4
MUTESAO MUTEAES
3 2
0 INT1
CS8427
1 0
INT0 TCBLD
DS477PP1