Cirrus Logic Crystal LAN CS8900A-CQ3 Manuals

Manuals and User Guides for Cirrus Logic Crystal LAN CS8900A-CQ3. We have 1 Cirrus Logic Crystal LAN CS8900A-CQ3 manual available for free PDF download: Product Data Sheet

Cirrus Logic Crystal LAN CS8900A-CQ3 Product Data Sheet

Cirrus Logic Crystal LAN CS8900A-CQ3 Product Data Sheet (128 pages)

Brand: Cirrus Logic | Category: Controller | Size: 2 MB

Table of Contents

Table of Contents
2
1 Introduction

8
- General Description
  8
  - Direct ISA-Bus Interface
    8
  - Integrated Memory
    8
  - Ethernet MAC Engine
    8
  - EEPROM Interface
    8
  - Complete Analog Front End
    8
- System Applications
  8
  - Motherboard Lans
    8
  - Ethernet Adapter Cards
    9
- Key Features and Benefits
  10
  - Very Low Cost
    10
  - High Performance
    10
  - Low Power and Low Noise
    10
  - Complete Support
    10
2 Pin Description

12
3 Functional Description

17
- Overview
  17
  - Configuration
    17
  - Packet Transmission
    17
  - Packet Reception
    17
- ISA Bus Interface
  18
  - Memory Mode Operation
    18
  - I/O Mode Operation
    18
  - Interrupt Request Signals
    18
  - DMA Signals
    18
- Reset and Initialization
  19
  - Reset
    19
    
    EEPROM Reset
    19
    
    External Reset, or ISA Reset
    19
    
    Hardware (HW) Standby or Suspend
    19
    
    Power-Down Reset
    19
    
    Power-Up Reset
    19
    
    Sof Tware (SW) Suspend
    19
    
    Software Initiated Reset
    19
  - Allowing Time for Reset Operation
    19
  - Initialization
    20
- Configurations with EEPROM
  21
- EEPROM Read-Out Completion
  24
- Programming the EEPROM
  24
  - EEPROM Commands
    24
  - EEPROM Command Execution
    24
  - Enabling Access to the EEPROM
    25
  - Writing and Erasing the EEPROM
    25
- Boot PROM Operation
  25
  - Accessing the Boot PROM
    25
  - Configuring the CS8900A for Boot PROM Operation
    25
- Low-Power Modes
  26
  - Hardware Standby
    26
  - Hardware Suspend
    26
  - Software Suspend
    27
- LED Outputs
  28
  - Lanled
    28
  - LINKLED or HC0
    28
  - BSTATUS or HC1
    28
  - LED Connection
    28
- Media Access Control
  28
  - Overview
    28
  - Frame Encapsulation and Decapsulation
    29
    
    Enforcing Minimum Frame Size
    29
    
    Reception
    29
    
    Transmission
    29
  - Transmit Error Detection and Handling
    30
    
    Jabber Error
    30
    
    Loss of Carrier
    30
    
    Out-Of-Window (Late) Collision
    30
    
    SQE Error
    30
    
    Transmit Collision
    30
    
    Transmit Underrun
    30
  - Receive Error Detection and Handling
    31
    
    CRC Error
    31
    
    Dribble Bits and Alignment Error
    31
    
    Extra Data
    31
    
    Runt Frame
    31
  - Media Access Management
    31
    
    Collision Avoidance
    31
    
    Two-Part Deferral
    31
    
    Collision Resolution
    32
    
    Normal Collisions
    32
    
    Simple Deferral
    32
    
    Backoff
    33
    
    Late Collisions
    33
    
    Modified Backoff
    33
    
    SQE Test
    33
    
    Standard Backoff
    33
- Encoder/Decoder (ENDEC)
  34
  - Encoder
    34
  - Carrier Detection
    34
  - Clock and Data Recovery
    34
    
    10BASE-T Only
    35
    
    Auionly
    35
    
    Auto-Select
    35
    
    Interface Selection
    35
  - 10BASE-T Transceiver
    35
    
    10BASE-T Filters
    35
    
    Extended Range
    36
    
    Link Pulse Detection
    36
    
    Receiver
    36
    
    Squelch Circuit
    36
    
    Transmitter
    36
    
    Collision Detection
    37
    
    Receive Polarity Detection and Correction
    37
  - Attachment Unit Interface (AUI)
    37
    
    AUI Transmitter
    37
    
    AUI Receiver
    38
    
    Collision Detection
    38
  - External Clock Oscillator
    38
4 Packetpage Architecture

39
- Packetpage Overview
  39
  - Integrated Memory
    39
  - Bus Interface Registers
    39
  - Status and Control Registers
    39
  - Initiate Transmit Registers
    39
  - Address Filter Registers
    39
  - Receive and Transmit Frame Locations
    39
- Packetpage Memory Map
  40
- Bus Interface Registers
  42
  - Product Identification Code
    42
  - I/O Base Address
    42
  - Interrupt Number
    43
  - DMA Channel Number
    43
  - DMA Start of Frame
    44
  - DMA Frame Count
    44
  - Rxdma Byte Count
    44
  - Memory Base Address
    44
  - Boot PROM Base Address
    45
  - Boot PROM Address Mask
    45
  - EEPROM Command
    46
  - EEPROM Data
    46
  - Receive Frame Byte Counter
    46
- Status and Control Registers
  47
- Initiate Transmit Registers
  71
  - Transmit Command Request - Txcmd
    71
  - Transmit Length
    71
- Address Filter Registers
  72
  - Logical Address Filter (Hash Table)
    72
  - Individual Address (IEEE Address)
    72
- Receive and Transmit Frame Locations
  73
  - Receive Packetpage Locations
    73
  - Transmit Locations
    73
- Eight and Sixteen Bit Transfers
  73
  - Transferring Odd-Byte-Aligned Data
    74
  - Random Access to CS8900A Memory
    74
- Memory Mode Operation
  74
- I/O Space Operation
  76
  - Receive/Transmit Data Ports 0 and 1
    76
  - Txcmd Port
    76
  - Txlength Port
    76
  - Interrupt Status Queue Port
    76
  - Packetpage Pointer Port
    76
  - Packetpage Data Ports 0 and 1
    77
  - I/O Mode Operation
    77
  - Basic I/O Mode Transmit
    77
  - Basic I/O Mode Receive
    77
  - Accessing Internal Registers
    78
  - Polling the CS8900A in I/O Mode
    78
5 Operation

79
- Managing Interrupts and Servicing the Interrupt Status Queue
  79
- Basic Receive Operation
  79
  - Overview
    79
  - Terminology: Packet, Frame, and Transfer
    81
    
    Frame
    81
    
    Packet
    81
    
    Transfer
    81
  - Receive Configuration
    81
    
    Choosing Which Frame Types to Accept
    81
    
    Configuring the Physical Interface
    81
    
    Choosing How to Transfer Frames
    82
    
    Selecting Which Events Cause Interrupts
    82
  - Receive Frame Pre-Processing
    83
    
    Destination Address Filtering
    83
    
    Acceptance Filtering
    84
    
    Early Interrupt Generation
    84
    
    Normal Interrupt Generation
    84
  - Held Vs. Dmaed Receive Frames
    84
  - Buffering Held Receive Frames
    84
  - Transferring Held Receive Frames
    86
  - Receive Frame Visibility
    86
  - Example of Memory Mode Receive Operation
    86
  - Receive Frame Byte Counter
    87
- Receive Frame Address Filtering
  87
  - Individual Address Frames
    88
  - Multicast Frames
    88
  - Broadcast Frames
    88
  - Configuring the Destination Address Filter
    88
  - Hash Filter
    89
    
    Hash Filter Operation
    89
  - Broadcast Frame Hashing Exception
    89
- Receive DMA
  90
- Auto-Switch DMA
  93
  - Overview
    93
  - Configuring the CS8900A for Auto-Switch DMA
    94
  - Auto-Switch DMA Operation
    94
  - DMA Channel Speed Vs. Missed Frames
    95
  - Exit from DMA
    95
  - Auto-Switch DMA Example
    96
- Streamtransfer
  96
  - Overview
    96
  - Configuring the CS8900A for Streamtransfer
    96
  - Streamtransfer Operation
    96
  - Keeping Streamtransfer Mode Active
    96
  - Example of Streamtransfer
    98
  - Receive DMA Summary
    98
- Transmit Operation
  99
  - Overview
    99
  - Transmit Configuration
    99
    
    Configuring the Physical Interface
    99
    
    Selecting Which Events Cause Interrupts
    99
  - Changing the Configuration
    99
  - Enabling CRC Generation and Padding
    100
  - Individual Packet Transmission
    100
  - Transmit in Poll Mode
    101
  - Transmit in Interrupt Mode
    101
  - Completing Transmission
    103
  - Rdy4Txnow Vs. Rdy4Tx
    103
  - Committing Buffer Space to a Transmit Frame
    103
  - Transmit Frame Length
    105
- Full Duplex Considerations
  105
- Auto-Negotiation Considerations
  105
6 Test Modes

106
- Loopback & Collision Diagnostic Tests
  106
- Internal Tests
  106
- External Tests
  106
- Loopback Tests
  106
- 10BASE-T Loopback and Collision Tests
  106
- AUI Loopback and Collision Tests
  106
- Boundary Scan
  107
  - Output Cycle
    107
  - Input Cycle
    107
  - Continuity Cycle
    108
7 Characteristics/Specifications

111
- Absolute Maximum Ratings
  111
- Recommended Operating Conditions
  111
- DC Characteristics
  111
- Switching Characteristics
  113
- 10Base-T Wiring
  120
- Aui Wiring
  121
- Quartz Crystal Requirements
  121
8 Physical Dimensions

122
9 Glossary of Terms

123
- Acronyms
  123
- Definitions
  124
- Acronyms Specific to the CS8900A
  125
- Terms Specific to the CS8900A
  125
- Suffixes Specific to the CS8900A
  126

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