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7.9 Interrupt 1 Mask (9)
7
6
TSLIPM
OSLIPM
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is considered
unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the
error is considered masked, meaning that its occurrence will not affect the INT pin or the status register. The bit po-
sitions align with the corresponding bits in the Interrupt 1 register. This register defaults to 00h.
7.10 Interrupt 1 Mode MSB (10) & Interrupt 1 Mode LSB (11)
7
6
TSLIP1
OSLIP1
TSLIP0
OSLIP0
The two Interrupt 1 Mode registers form a two bit code for each Interrupt 1 function. This code determines whether
the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition, or on the
continuing occurrence of the interrupt condition. These registers default to 00h.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
7.11 Interrupt 2 Mask (12)
7
6
0
0
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is considered
unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the
error is considered masked, meaning that its occurrence will not affect the INT pin or the status register. The bit po-
sitions align with the corresponding bits in the Interrupt 2 register. This register defaults to 00h.
7.12 Interrupt 2 Mode MSB (13) & Interrupt 2 Mode LSB (14)
7
6
0
0
0
0
The two Interrupt 2 Mode registers form a two bit code for each Interrupt 2 register function. This code determines
whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition, or
on the continuing occurrence of the interrupt condition. These registers default to 00h.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
DS477PP1
5
4
0
0
5
4
0
0
0
0
5
4
0
0
5
4
0
0
0
0
3
2
0
DETCM
3
2
0
DETC1
0
DETC0
3
2
DETUM
EFTUM
3
2
DETU1
EFTU1
DETU0
EFTU0
CS8427
1
0
EFTCM
RERRM
1
0
EFTC1
RERR1
EFTC0
RERR0
1
0
QCHM
0
1
0
QCH1
0
QCH0
0
33
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