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96 kHz Digital Audio Interface Transceiver
Features
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Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF compatible transceiver
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+3V to +5V Digital Supply
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Flexible 3-wire serial digital I/O ports
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Adjustable sample rate up to 96 kHz
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Low jitter clock recovery
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Pin and microcontroller read/write access to
Channel Status and User data
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Microcontroller and stand-alone modes
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Differential cable driver & receiver
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On-chip Channel Status and User data buffer
memory provides block reads & writes
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OMCK System Clock Mode
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Decodes Audio CD Q sub-code
I
VA+ AGND FILT
ILRCK
Serial
ISCLK
Audio
Input
SDIN
RXP
Receiver
RXN
Misc.
Control
H/S
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
RERR
RMCK
Clock &
AES3
Data
S/PDIF
Recovery
Decoder
RST
EMPH U TCBL SDA/
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
General Description
The CS8427 is a stereo digital audio transceiver with
AES3 and serial digital audio inputs, AES3 and serial
digital audio outputs, along with comprehensive control
ability via a 4-wire microcontroller port. Channel status
and user data are assembled in block sized buffers,
making read/modify/write cycles easy.
A low jitter clock recovery mechanism yields a very
clean recovered clock from the incoming AES3 stream.
Target applications include CD-R, DAT, MD and VTR
equipment, mixing consoles, digital audio transmission
equipment, high quality D/A and A/D converters, effects
processors, set-top box and computer audio systems.
ORDERING INFO
CS8427-CS
CS8427-CZ
CDB8427
C & U bit
Data
Buffer
Control
Port &
Registers
SCL/
AD1/
AD0/
CDOUT
CCLK
CDIN
CS
Copyright Cirrus Logic, Inc. 1999
(All Rights Reserved)
CS8427
28-pin SOIC, -10 to +70°C
28-pin TSSOP, -10 to +70°C
Evaluation Board
VD+ DGND
Serial
Audio
Output
AES3
Driver
S/PDIF
Encoder
Output
Clock
Generator
INT
OMCK
OLRCK
OSCLK
SDOUT
TXP
TXN
NOV '99
DS477PP1
1
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Table of Contents
Related Manuals for Cirrus Logic Crystal CS8427 Series
Summary of Contents for Cirrus Logic Crystal CS8427 Series
- Page 1 CDOUT CCLK CDIN This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. NOV ‘99 Copyright Cirrus Logic, Inc. 1999 P.O. Box 17847, Austin, Texas 78760 DS477PP1...
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Page 2: Table Of Contents
(electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture... - Page 3 CS8427 7.4 Clock Source Control (4) ....................29 7.5 Serial Audio Input Port Data Format (5) ................30 7.6 Serial Audio Output Port Data Format (6) ................ 31 7.7 Interrupt 1 Status (7) (Read Only) ..................32 7.8 Interrupt 2 Status (8) (Read Only) ..................32 7.9 Interrupt 1 Mask (9) ......................
- Page 4 CS8427 LIST OF FIGURES Figure 1. Audio Port Master Mode Timing..................7 Figure 2. Audio Port Slave Mode and Data Input Timing ..............7 Figure 3. SPI Mode timing....................... 8 Figure 4. I C Mode timing ....................... 9 Figure 5. Recommended Connection Diagram for Software Mode..........10 Figure 6.
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Page 5: Characteristics And Specifications
CS8427 1. CHARACTERISTICS AND SPECIFICATIONS POWER AND THERMAL CHARACTERISTICS (AGND, DGND = 0V, all voltages with respect to ground) Parameter Symbol Units Power Supply Voltage 3.0/5.0 Supply Current at 48kHz frame rate VD+ = 3V VD+ = 5V Supply Current at 96kHz frame rate VD+ = 3V VD+ = 5V Supply Current in power down... -
Page 6: Switching Characteristics
CS8427 SWITCHING CHARACTERISTICS = 25 °C; VA+ = 5V, VD+ = 3/5V, ±10%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C = 20pF) Parameter Symbol Units µ s RST pin Low Pulse Width OMCK Frequency for OMCK = 512*Fso 55.3 OMCK Low and High Width for OMCK = 512*Fso OMCK Frequency for OMCK = 384*Fso... -
Page 7: Switching Characteristics - Serial Audio Ports
CS8427 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS = 25 °C; VA+ = 5V, VD+ = 3/5V, ±10%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C = 20pF) Parameter Symbol Units OSCLK Active Edge to SDOUT Output Valid (Note 4) SDIN Setup Time Before ISCLK Active Edge (Note 4) SDIN Hold Time After ISCLK Active Edge... -
Page 8: Switching Characteristics - Control Port - Spi Mode
CS8427 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE = 25 °C; VA+ = 5V, VD+ = 3/5V, ±10%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C = 20pF) Parameter Symbol Units CCLK Clock Frequency (Note 8) µ s CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time... -
Page 9: Switching Characteristics - Control Port - I 2 C ® Mode
CS8427 ® SWITCHING CHARACTERISTICS - CONTROL PORT - I MODE (Note 11, T 25 °C; VA+ = 5V, VD+ = 3/5V, ±10%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C = 20pF) Parameter Symbol Units SCL Clock Frequency µ... -
Page 10: Typical Connection Diagram
CS8427 2. TYPICAL CONNECTION DIAGRAM Ferrite * Bead +3 to +5 V µ Analog Digital 0.1 F Supply * Supply µ 0.1 F AES3/ AES3/ Cable Cable SPDIF SPDIF Termination Interface Source Equipment CS8427 ILRCK OLRCK 3-wire Serial 3-wire Serial Audio Input ISCLK OSCLK... -
Page 11: General Description
CS8427 3. GENERAL DESCRIPTION To guarantee system compliance, the proper stan- dards documents should be obtained. The latest The CS8427 is an AES3 transceiver intended to be AES3 standard should be obtained from the Audio used in digital audio systems. Such systems include Engineering Society or ANSI, the latest IEC60958 digital mixing consoles, effects processors, tape re- standard from the International Electrotechnical... -
Page 12: Aes3 Transmitter And Receiver
CS8427 Figure 12 shows the entire data path clocked via the wide range of input sample rates with no external PLL generated recovered clock. Figure 13 illus- component changes. If the sample rate of the input trates a standard AES3 receiver function. Figure 14 subsequently changes, for example in a varispeed shows a standard AES3 transmitter function. -
Page 13: Figure 6. Jitter Attenuation Characteristics Of Pll With 8 To 96 Khz Fs Filter Components-Aes3
CS8427 Digital Bode plot Digital Bode plot Frequency (Hz) Frequency (Hz) Figure 6. Jitter Attenuation Characteristics of PLL with Figure 7. Jitter Attenuation Characteristics of PLL with 8 to 96 kHz Fs Filter Components-AES3 32 to 96 kHz Fs Filter Components-AES3 RFILT (k Ω... -
Page 14: Table 2. Pll External Components Using Ilrck
CS8427 Digital Bode plot Digital Bode plot Frequency (Hz) Frequency (Hz) Figure 8. Jitter Attenuation Characteristics of PLL with Figure 9. Jitter Attenuation Characteristics of PLL with 8 to 96 kHz Fs Filter Components-ILRCK 32 to 96 kHz Fs Filter Components-ILRCK RFILT (k Ω... -
Page 15: Error Reporting And Hold Function
CS8427 4.2.4 Error Reporting and Hold Function 4.2.5 Channel Status Data Handling While decoding the incoming AES3 data stream, The first two bytes of the Channel Status block are the CS8427 can identify several kinds of error, in- decoded into the Receiver Channel Status register. dicated in the Receiver Error register. -
Page 16: Non-Audio Auto-Detection
CS8427 If the incoming user data bits have been encoded as The transmitter clock may be derived from the Q-channel subcode, the data is decoded and pre- clock input pin OMCK, or from the incoming data. sented in ten consecutive register locations. An in- If OMCK is asynchronous to the data source, an in- terrupt may be enabled to indicate the decoding of terrupt bit is provided that will go high every time... -
Page 17: Txn And Txp Drivers
CS8427 4.3.2 TXN and TXP Drivers 4.4.1 Receiver Mono Mode The line drivers are low skew, low impedance, dif- The receiver mono mode effectively doubles the ferential outputs capable of driving cables directly. input frame rate, Fsi. The clock output on the Both drivers are set to ground during reset (RST = RMCK pin tracks Fsi, and thus is doubled in fre- low), when no AES3 transmit clock is provided,... -
Page 18: Figure 10. Software Mode Audio Data Flow Switching Options
CS8427 ILRCK OLRCK Serial Serial Audio ISCLK OSCLK Audio Output SDIN Input SDOUT AESBP TXOFF AES3 AES3 Receiver Encoder Figure 10. Software Mode Audio Data Flow Switching Options SOMS ILRCK OLRCK Serial Serial ISCLK OSCLK Audio Audio SDIN Input Output SDOUT Channel Status... -
Page 19: Figure 12. Aes3 Input To Serial Audio Output, Serial Audio Input To Aes3 Out
CS8427 ILRCK SDOUT OSCLK OLRCK SDIN ISCLK Serial Serial AES3 Serial OLRCK Audio Audio Output Input Rx & Audio OSCLK Decode Output SDOUT AES3 AES3 Rx & Encoder Decode & Driver RMCK RMCK Data Flow Control Bits Clock Source Control Bits Data Flow Control Bits Clock Source Control Bits TXD1-0:... -
Page 20: Figure 15. Aes3 Receiver Timing For U Pin Output Data
CS8427 VLRCK Output VLRCK is a virtual word clock, which may not exist, but is used to illustrate the U timing. VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate. If the serial audio output port is in master mode, VLRCK = OLRCK. If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required. -
Page 21: Figure 17. Serial Audio Input Example Formats
CS8427 Right Left ILRCK Left ISCLK Justified SDIN (In) Left Right ILRCK ISCLK (In) SDIN Right Left ILRCK Right ISCLK Justified (In) SDIN SIMS* SISF* SIRES1/0* SIJUST* SIDEL* SISPOL* SILRPOL* Left Justified Right Justified X = don’t care to match format, but does need to be set to the desired setting S can accept an arbitrary number of bits, determined by the number of ISCLK cycles * See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit Figure 17. -
Page 22: Figure 18. Serial Audio Output Example Formats
CS8427 Right OLRCK Left Left Justified OSCLK (Out) SDOUT Left Right OLRCK OSCLK (Out) SDOUT Right OLRCK Left Right Justified OSCLK (Out) SDOUT Right OLRCK Left AES3 Direct OSCLK (Out) SDOUT SOMS* SOSF* SORES1/0* SOJUST* SODEL* SOSPOL* SOLRPOL* Left Justified Right Justified AES3 Direct X = don’t care to match format, but does need to be set to the desired setting... -
Page 23: Control Port Description And Timing
CS8427 5. CONTROL PORT DESCRIPTION zero, the MAP will stay constant for successive AND TIMING read or writes. If INCR is set to a 1, then the MAP will autoincrement after each byte is read or writ- The control port is used to access the registers, al- ten, allowing block reads or writes of successive lowing the CS8427 to be configured for the desired registers. -
Page 24: Interrupts
CS8427 knowledge bit, ACK, which is output from the ups with multiple peripherals connected to the mi- CS8427 after each input byte is read. The ACK bit crocontroller interrupt input pin. is input to the CS8427 from the microcontroller af- Many conditions can cause an interrupt, as listed in ter each transmitted byte. -
Page 25: Control Port Register Summary
CS8427 6. CONTROL PORT REGISTER SUMMARY Addr Function Reserved Control 1 SWCLK VSET MUTESAO MUTEAES INT1 INT0 TCBLD Control 2 HOLD1 HOLD0 RMCKF MMTCS MMTLR Data Flow Control TXOFF AESBP TXD1 TXD0 SPD1 SPD0 Clock Source Control CLK1 CLK0 OUTC RXD1 RXD0 Serial Input Format... -
Page 26: Control Port Register Bit Definitions
CS8427 7. CONTROL PORT REGISTER BIT DEFINITIONS 7.1 Control 1 (1) SWCLK VSET MUTESAO MUTEAES INT1 INT0 TCBLD SWCLK - Controls output of OMCK on RMCK when PLL loses lock Default = ‘0’ 0 - RMCK default function 1 - OMCK output on RMCK pin VSET - Transmitted V bit level Default = ‘0’... -
Page 27: Control 2 (2)
CS8427 7.2 Control 2 (2) HOLD1 HOLD0 RMCKF MMTCS MMTLR HOLD1:HOLD0 - Determine how received audio sample is affected when a receiver error occurs Default = ‘00’ 00 - Hold the last valid audio sample 01 - Replace the current audio sample with 00 (mute) 10 - Do not change the received audio sample 11 - Reserved RMCKF - Select recovered master clock output pin frequency. -
Page 28: Data Flow Control (3)
CS8427 7.3 Data Flow Control (3) TXOFF AESBP TXD1 TXD0 SPD1 SPD0 The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audio Input Port, Serial Audio Output Port, AES3 receiver, and AES3 transmitter. In conjunction with the Clock Source Control regis- ter, multiple Receiver/Transmitter/Transceiver modes may be selected. -
Page 29: Clock Source Control (4)
CS8427 7.4 Clock Source Control (4) CLK1 CLK0 OUTC RXD1 RXD0 This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var- ious Receiver/Transmitter/Transceiver modes may be selected. RUN - Controls the internal clocks, allowing the CS8427 to be placed in a “powered down”, low current consumption, state. -
Page 30: Serial Audio Input Port Data Format (5)
CS8427 7.5 Serial Audio Input Port Data Format (5) SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL SIMS - Master/Slave Mode Selector Default = ‘0’ 0 - Serial audio input port is in slave mode 1 - Serial audio input port is in master mode SISF - ISCLK frequency (for master mode) Default = ‘0’... -
Page 31: Serial Audio Output Port Data Format (6)
CS8427 7.6 Serial Audio Output Port Data Format (6) SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL SOMS - Master/Slave Mode Selector Default = ‘0’ 0 - Serial audio output port is in slave mode 1 - Serial audio output port is in master mode SOSF - OSCLK frequency (for master mode) Default = ‘0’... -
Page 32: Interrupt 1 Status (7) (Read Only)
CS8427 7.7 Interrupt 1 Status (7) (Read Only) TSLIP OSLIP DETC EFTC RERR For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. -
Page 33: Interrupt 1 Mask (9)
CS8427 7.9 Interrupt 1 Mask (9) TSLIPM OSLIPM DETCM EFTCM RERRM The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the status register. -
Page 34: Receiver Channel Status (15) (Read Only)
CS8427 7.13 Receiver Channel Status (15) (Read Only) AUX3 AUX2 AUX1 AUX0 AUDIO COPY ORIG The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control Register. AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, decoded according to IEC60958 and AES3. -
Page 35: Receiver Error (16) (Read Only)
CS8427 7.14 Receiver Error (16) (Read Only) QCRC CCRC UNLOCK CONF This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still true. -
Page 36: Receiver Error Mask (17)
CS8427 7.15 Receiver Error Mask (17) QCRCM CCRCM UNLOCKM CONFM BIPM PARM The bits in this register serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit. -
Page 37: User Data Buffer Control (19)
CS8427 7.17 User Data Buffer Control (19) UBM1 UBM0 DETUI EFTUI UD - User data pin (U) direction specifier Default = ‘0’ 0 - The U pin is an input. The U data is latched in on both rising and falling edges of OLRCK. -
Page 38: Q-Channel Subcode Bytes 0 To 9 (20 - 29) (Read Only)
CS8427 7.18 Q-Channel Subcode Bytes 0 to 9 (20 - 29) (Read Only) The following 10 registers contain the decoded Q-channel subcode data ADDRESS ADDRESS ADDRESS ADDRESS CONTROL CONTROL CONTROL CONTROL TRACK TRACK TRACK TRACK TRACK TRACK TRACK TRACK INDEX INDEX INDEX INDEX... -
Page 39: Pin Description - Software Mode
CS8427 8. PIN DESCRIPTION - SOFTWARE MODE SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN EMPH AGND DGND FILT OMCK RMCK RERR SDOUT ILRCK OLRCK ISCLK OSCLK SDIN TCBL * Pins which remain the same function in all modes. + Pins which require a pull up or pull down resistor to select the desired startup option. - Page 40 CS8427 RERR Receiver Error (Output) - When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: validity, parity error, bi-phase coding error, confidence, QCRC and CCRC errors, as well as loss of lock in the PLL.
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Page 41: Hardware Mode Description
CS8427 9. HARDWARE MODE DESCRIPTION PH/U and AUDIO/V pins. Figure 15 shows the timing requirements. Hardware mode is selected by connecting the H/S pin to ‘1’. Hardware Mode data flow is shown in The APMS pin allows the serial audio input port to Figure 21. -
Page 42: Table 4. Hardware Mode Start-Up Options
CS8427 SDOUT RMCK RERR ORIG COPY Function Serial Output Port is Slave Serial Output Port is Master Mode A: C transmitted data is copied from received data, U and V =0, received PRO, EMPH, AUDIO is visible Mode B: CUV transmitted data is input serially on pins, received PRO, EMPH and AUDIO is not visible Serial Input &... -
Page 43: Pin Description - Hardware Mode
CS8427 10. PIN DESCRIPTION - HARDWARE MODE COPY ORIG DGND2 VD2+ EMPH/U AGND DGND FILT APMS PRO/C RMCK 10*+ AUDIO/V RERR 11*+ +*18 SDOUT ILRCK OLRCK ISCLK OSCLK SDIN TCBL * Pins which remain the same function in all modes. + Pins which require a pull up or pull down resistor to select the desired startup option. - Page 44 CS8427 TCBL Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block.
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Page 45: Applications
CS8427 11. APPLICATIONS CS8427. This is useful when other CS84XX family members are resident in the same system, allowing 11.1 Reset, Power Down and Start-up common software modules. When RST is low, the CS8427 enters a low power The CS8427 four bit revision code is also available. mode and all internal states are reset, including the This allows the software driver for the CS8427 to control port and registers, and the outputs are mut-... -
Page 46: Synchronization Of Multiple Cs8427S
CS8427 11.4 Synchronization of Multiple CS8427s The serial audio output ports of multiple CS8427s can be synchronized if all devices share the same master clock, OSCLK, OLRCK, and RST line and leave the reset state on the same master clock fall- ing edge. -
Page 47: Package Dimensions
CS8427 12. PACKAGE DIMENSIONS 28L SOIC (300 MIL BODY) PACKAGE DRAWING ∝ SEATING PLANE INCHES MILLIMETERS 0.093 0.104 2.35 2.65 0.004 0.012 0.10 0.30 0.013 0.020 0.33 0.51 0.009 0.013 0.23 0.32 0.697 0.713 17.70 18.10 0.291 0.299 7.40 7.60 0.040 0.060 1.02... - Page 48 CS8427 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING ∝ END VIEW SEATING PLANE SIDE VIEW 1 2 3 TOP VIEW INCHES MILLIMETERS NOTE 0.043 1.10 0.002 0.006 0.05 0.15 0.034 0.037 0.85 0.95 0.008 0.012 0.19 0.30 0.303 0.311 7.70 7.90 0.248 0.256...
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Page 49: Appendix A: External Aes3/Spdif/Iec60958 Transmitter And Receiver Components
CS8427 provides a 5 volt peak-to-peak signal into a 110 Ω 13. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 load. Lastly, the two output pins should be attached TRANSMITTER AND RECEIVER to an XLR connector with male pins and a female COMPONENTS shell, and with pin 1 of the connector grounded. This section details the external components re- In the case of consumer use, the IEC60958 specifi- quired to interface the AES3 transmitter and re-... -
Page 50: Aes3 Receiver External Components
CS8427 13.2 AES3 Receiver External Components the shield of the cable that could result when boxes with different ground potentials are connected. The CS8427 AES3 receiver is designed to accept Generally, it is good practice to ground the shield both the professional and consumer interfaces. The to the chassis of the transmitting unit, and connect digital audio specifications for professional use call the shield through a capacitor to chassis ground at... -
Page 51: Appendix B: Channel Status And User Data Buffer Management
CS8427 14. APPENDIX B: CHANNEL STATUS port address 32) is the consumer/professional bit AND USER DATA BUFFER for channel status block A. MANAGEMENT The first buffer, D, accepts incoming C data from The CS8427 has a comprehensive channel status the AES receiver. The 2nd buffer, E, accepts entire (C) and user (U) data buffering scheme, which al- blocks of data from the D buffer. -
Page 52: Reserving The First 5 Bytes In The E Buffer
CS8427 havior of the buffers with the selected audio data for users who want to transmit certain channel sta- flow. For example, if the audio data flow is serial tus settings which are different from the incoming port in to AES3 out, then it is necessary to inhibit settings. -
Page 53: Channel Status Data E Buffer Access
CS8427 14.1.4 Channel Status Data E Buffer In this mode, a read will cause the CS8427 to out- put two bytes from its control port. The first byte Access out will represent the A channel status data, and the The E buffer is organized as 24 x 16-bit words. For 2nd byte will represent the B channel status data.
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