Clock Source Control (4) - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

7.4 Clock Source Control (4)

7 6
0 RUN
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var-
ious Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8427 to be placed in a "powered down", low current
consumption, state.
Default = '0'
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
control port is operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
1 - Normal part operation. This bit must be written to the 1 state to allow the CS8427
to begin operation. All input clocks should be stable in frequency and phase when
RUN is set to 1.
CLK1:0 - Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits
are changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start
the CS8427 (RUN = 1).
Default = '00'
00 - OMCK frequency is 256*Fso
01 - OMCK frequency is 384*Fso
10 - OMCK frequency is 512*Fso
11 - Reserved
OUTC - Output Time Base
Default = '0'
0 - OMCK input pin, modified by the selected divide ratio bits CLK1:0.
1 - Recovered Input Clock
INC - Input Time Base Clock Source
Default = '0'
0 - Recovered Input Clock
1 - OMCK input pin, modified by the selected divide ratio bits CLK1:0.
RXD1:0 - Recovered Input Clock Source
Default = '00'
00 - 256*Fsi, where Fsi is derived from the ILRCK pin (only possible when the
serial audio input port is in slave mode)
01 - 256*Fsi, where Fsi is derived from the AES3 input frame rate
10 - Bypass the PLL and apply an external 256*Fsi clock via the RMCK pin. The AES3
receiver is held in synchronous reset. This setting is useful to prevent UNLOCK
interrupts when using an external RMCK and inputting data via the serial audio input port.
11 - Bypass the PLL and apply an external 256*Fsi clock via the RMCK pin. The AES3
receiver is operational.
DS477PP1
5 4
CLK1 CLK0
3 2
OUTC INC
CS8427
1 0
RXD1 RXD0
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