Reserving The First 5 Bytes In The E Buffer; Serial Copy Management System (Scms); Figure 30. Flowchart For Reading The E Buffer; Figure 31. Flowchart For Writing The E Buffer - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

havior of the buffers with the selected audio data
flow. For example, if the audio data flow is serial
port in to AES3 out, then it is necessary to inhibit
"D toE" transfers, since these would overwrite the
desired transmit C data with invalid data.
Flowcharts for reading and writing to the E buffer
are shown in Figures 30 and 31. For reading, since
a D to E interrupt just occurred, then there a sub-
stantial time interval until the next D to E transfer
(approximately 24 frames worth of time). This is
usually plenty of time to access the E data without
having to inhibit the next transfer.
For writing, the sequence starts after a E to F trans-
fer, which is based on the output timebase. Since a
D to E transfer could occur at any time (this is
based on the input timebase), then it is important to
inhibit D to E transfers while writing to the E buffer
until all writes are complete. Then wait until the
next E to F transfer occurs before enabling D to E
transfers. This ensures that the data written to the E
buffer actually gets transmitted and not overwritten
by a D to E transfer.
If the channel status block to transmit indicates
PRO mode, then the CRCC byte is automatically
calculated by the CS8427, and does not have to be
written into the last byte of the block by the host
microcontroller.
14.1.2 Reserving the first 5 bytes in the E
buffer
D to E buffer transfers periodically overwrite the
data stored in the E buffer. This can be a problem
D to E interrupt occurs
Optionally set D to E inhibit
If set, clear D to E inhibit
Return

Figure 30. Flowchart for Reading the E Buffer

52
Read E data
for users who want to transmit certain channel sta-
tus settings which are different from the incoming
settings. In this case, the user would have to super-
impose his settings on the E buffer after every D to
E overwrite.
To avoid this problem, the CS8427 has the capabil-
ity of reserving the first 5 bytes of the E buffer for
user writes only. When this capability is in use, in-
ternal D to E buffer transfers will NOT affect the
first 5 bytes of the E buffer. Therefore, the user can
set values in these first 5 E bytes once, and the set-
tings will persist until the next user change. This
mode is enabled via the Channel Status Data Buffer
Control register.
14.1.3 Serial Copy Management System
(SCMS)
In software mode, the CS8427 allows read/modi-
fy/write access to all the channel status bits. For
consumer mode SCMS compliance, the host mi-
crocontroller needs to read and manipulate the Cat-
egory Code, Copy bit and L bit appropriately.
In hardware mode, the SCMS protocol can be fol-
lowed by either using the COPY and ORIG input
pins, or by using the C bit serial input pin. These
options are documented in the hardware mode sec-
tion of this data sheet.
E to F interrupt occurs
Optionally set E to F inhibit
If set, clear E to F inhibit
Wait for E to F transfer
Clear D to E inhibit
Return

Figure 31. Flowchart for Writing the E Buffer

CS8427
Set D to E inhibit
Write E data
DS477PP1