Cirrus Logic Crystal CS8427 Series Preliminary Product Information page 40

RERR 11 Receiver Error (Output) - When high, indicates a problem with the operation of the AES3 receiver. The
status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause
RERR to go high are: validity, parity error, bi-phase coding error, confidence, QCRC and CCRC errors,
as well as loss of lock in the PLL. Each condition may be optionally masked from affecting the RERR pin
using the Receiver Error Mask Register. The RERR pin tracks the status of the unmasked errors: the pin
goes high as soon as an unmasked error occurs and goes low immediately when all unmasked errors go
away
ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin.
ISCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
SDIN 14 Serial Audio Data Port (Input) - Audio data serial input pin.
TCBL 15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
OSCLK 16 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
OLRCK 17 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs)
SDOUT 18 Serial Audio Output Data (Output) - Audio data serial output pin
INT 19 Interrupt (Output) -Indicates errors and key events during the operation of the CS8427. All bits affecting
INT may be unmasked through bits in the control registers. The condition(s) that initiated interrupt are
readable through a control register. The polarity of the INT output, as well as selection of a standard or
open drain output, is set via a control register. Once set true, the INT pin goes false only after the inter-
rupt status registers have been read and the interrupt status bits have returned to zero
U 20 User Data (Output) -
transmitter, see Figure 15 for timing information. Alternatively, the U pin may be set to output
User data from the AES3 receiver, see Figure 15 for timing information. If not driven, a 47k Ω
pull-down resistor is recommended for the U pin, since the default state of the UD direction bit
sets the U pin as an input. The pull-down resistor ensures that the transmitted user data will be
zero. If the U pin is always set to be an output, thereby causing the U bit manager to be the
source of the U data, then the resistor is not necessary. The U pin should not be tied directly to
ground, in case it is programmed to be an output, and subsequently tries to output a logic
high. This situation may affect the long term reliability of the device. If the U pin is driven by a
logic level output, then a 100 Ω series resistor is recommended.
OMCK 21 System Clock (Input) - When the OMCK System Clock Mode is enabled by the SWCLK bit in the Con-
trol 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as reference sig-
nal for OMCK/RMCK ratio expressed in register 30
DGND 22 Digital Ground (Input) - Ground for the digital section. DGND should be connected to the same ground
as AGND
VD+ 23 Positive Digital Power (Input) - Typically +3 to +5V.
24 Hardware/Software Mode Control (Input) - Determines the method of controlling the operation of the
H/S
CS8427, and the method of accessing CS and U data. In software mode, device control and CS and U
data access is primarily via the control port, using a microcontroller. Hardware mode provides an alter-
nate mode of operation and access to the CS and U data via dedicated pins. This pin should be perma-
nently tied to VD+ or DGND
TXN 25 Differential Line Driver (Output) - Drivers transmit AES3 data and are pulled low while the CS8427 is in
TXN the reset state.
26
AD1/CDIN 27 Address Bit 1 (I2C) / Serial Control Data in (SPI) (Input) - In I
SPI mode, CDIN is the input data line for the control port interface
SCL/CCLK 28 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and
out of the CS8427. In I
40
.
May optionally be used to input User data for transmission by the AES3
2
C mode, SCL requires an external pull-up resistor to VD+
2
C mode, AD1 is a chip address pin. In
CS8427
DS477PP1