Control Port Register Summary; Memory Address Pointer (Map); Table 3. Control Register Map Summary - Cirrus Logic Crystal CS8427 Series Preliminary Product Information

6. CONTROL PORT REGISTER SUMMARY

Addr Function
0 Reserved
1 Control 1
2 Control 2
3 Data Flow Control
4 Clock Source Control
5 Serial Input Format
6 Serial Output Format
7 Interrupt 1 Status
8 Interrupt 2 Status
9 Interrupt 1 Mask
10 Interrupt 1 Mode (MSB)
11 Interrupt 1 Mode (LSB)
12 Interrupt 2 Mask
13 Interrupt 2 Mode (MSB)
14 Interrupt 2 Mode (LSB)
15 Receiver CS Data
16 Receiver Errors
17 Receiver Error Mask
18 CS Data Buffer Control
19 U Data Buffer Control
20-29 Q sub-code Data
30 OMCK/RMCK Ratio
31 Reserved
32-55 C or U Data Buffer
127 ID and Version

6.1 Memory Address Pointer (MAP)

7 6
INCR MAP6
INCR - Auto Increment Address Control Bit
Default = '0'
0 - Disable
1 - Enable
MAP6:MAP0 - Register address
Note: Reserved registers must not be written to during normal operation. Some reserved registers are used for test
modes, which can completely alter the normal operation of the CS8427.
DS477PP1
7 6
0 0
SWCLK VSET MUTESAO
0 HOLD1 HOLD0
0 TXOFF AESBP
0 RUN CLK1
SIMS SISF SIRES1
SOMS SOSF SORES1
TSLIP OSLIP
0 0
TSLIPM OSLIPM
TSLIP1 OSLIP1
TSLIP0 OSLIP0
0 0
0 0
0 0
AUX3 AUX2 AUX1
0 QCRC CCRC
0 QCRCM CCRCM
0 0 BSEL
0 0
ORR7 ORR6 ORR5
0 0
ID3 ID2

Table 3. Control Register Map Summary

5 4
MAP5 MAP4
5 4 3
0 0 0
MUTEAES 0
RMCKF MMR
TXD1 TXD0
CLK0 OUTC
SIRES0 SIJUST
SORES0 SOJUST
0 0 0
0 0 DETU
0 0 0
0 0 0
0 0 0
0 0 DETUM
0 0 DETU1
0 0 DETU0
AUX0 PRO
UNLOCK V
UNLOCKM VM
CBMR DETCI
0 UD UBM1
ORR4 ORR3
0 0 0
ID1 ID0 VER3
3 2
MAP3 MAP2
CS8427
2 1 0
0 0 0
INT1 INT0 TCBLD
MMT MMTCS MMTLR
SPD1 SPD0 0
INC RXD1 RXD0
SIDEL SISPOL SILRPOL
SODEL SOSPOL SOLRPOL
DETC EFTC RERR
EFTU QCH 0
DETCM EFTCM RERRM
DETC1 EFTC1 RERR1
DETC0 EFTC0 RERR0
EFTUM QCHM 0
EFTU1 QCH1 0
EFTU0 QCH0 0
AUDIO COPY ORIG
CONF BIP PAR
CONFM BIPM PARM
EFTCI CAM CHS
UBM0 DETUI EFTUI
ORR2 ORR1 ORR0
0 0 0
VER2 VER1 VER0
1 0
MAP1 MAP0
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