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CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Features
!
Single-Chip IEEE 802.3 Physical Interface IC
for 100BASE-TX, 100BASE-FX and
10BASE-T
!
Adaptive Equalizer provides Extended
Length Operation (>160 m) with Superior
Noise Immunity and NEXT Margin
!
Extremely Low Transmit Jitter (<400 ps)
!
Low Common Mode Noise on TX Driver for
Reduced EMI Problems
!
Integrated RX and TX Filters for 10BASE-T
!
Compensation for Back-to-Back "Killer
Packets"
!
Digital Interfaces Supported
– Media Independent Interface (MII) for
100BASE-X and 10BASE-T
– Repeater 5-bit code-group interface
(100BASE-X)
– 10BASE-T Serial Interface
!
Register Set Compatible with DP83840A
!
IEEE 802.3 Auto-Negotiation with Next Page
Support
TX_EN
TX_ER/TXD4
TXD[3:0]
TX_CLK
MDC
MII_IRQ
MDIO
RX_ER/RXD4
RX_DV
RXD[3:0]
RX_CLK
RX_EN
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS8952 10BaseT/100Base-X
Transceiver
4B/5B
Encoder
10/100
4B/5B
Decoder
M
U
CRS
X
COL
MII
Control/Status
Registers
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
!
Six LED drivers (LNK, COL, FDX, TX, RX,
and SPD)
!
Low power (135 mA Typ) CMOS design
operates on a single 5 V supply
Description
The CS8952 uses CMOS technology to deliver a high-
performance, low-cost 100BASE-X/10BASE-T Physical
Layer (PHY) line interface. It makes use of an adaptive
equalizer optimized for noise and near end crosstalk
(NEXT) immunity to extend receiver operation to cable
lengths exceeding 160 m. In addition, the transmit cir-
cuitry has been designed to provide extremely low
transmit jitter (<400 ps) for improved link partner perfor-
mance. Transmit driver common mode noise has been
minimized to reduce EMI for simplified FCC certification.
The CS8952 incorporates a standard Media Indepen-
dent Interface (MII) for easy connection to a variety of 10
and 100 Mb/s Media Access Controllers (MACs). The
CS8952 also includes a pseudo-ECL interface for use
with 100Base-FX fiber interconnect modules.
ORDERING INFORMATION
CS8952-CQ
CDB8952
Manchester
10BaseT
Encoder
Filter
MLT-3
Slew Rate
Scrambler
Encoder
Control
Fiber NRZI
Interface
Fiber NRZI
Interface
MLT-3
100BaseT
Descrambler
Decoder
Slicer
Manchester
10BaseT
Decoder
Slicer
Link
Timing
Auto
Management
Recovery
Negotiation
Copyright Cirrus Logic, Inc. 2001
(All Rights Reserved)
CS8952
0 to 70 °C
100-pin TQFP
Evaluation Board
10/100
M
TX+,
U
TX-
X
TX_NRZ+,
ECL Driver
TX_NRZ-
RX_NRZ+,
ECL Receiver
RX_NRZ-
Adaptive Eq. &
Baseline Wander
Compensation
RX+,
RX-
10BaseT
Filter
LED1
LED2
LED
LED3
Drivers
LED4
LED5
DS206PP3
1
OCT '01
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Related Manuals for Cirrus Logic CS8952
Summary of Contents for Cirrus Logic CS8952
- Page 1 LED4 LED5 This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2001 P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved) DS206PP3 (512) 445 7222 FAX: (512) 445 7581 OCT ‘01...
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Page 2: Table Of Contents
Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. - Page 3 Configuration At Power-up/Reset Time............... 30 Configuration Via Control Pins ................30 Configuration via the MII ..................30 CS8952 REGISTERS ....................31 Basic Mode Control Register - Address 00h ............. 32 Basic Mode Status Register - Address 01h ............34 PHY Identifier, Part 1 - Address 02h ..............36 PHY Identifier, Part 2 - Address 03h ..............
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Page 4: Specifications And Characteristics
CS8952 SPECIFICATIONS AND CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) Parameter Symbol Unit Power Supply -0.3 -0.3 DD_MII Input Current Except Supply Pins +/-10.0 Input Voltage -0.3 + 0.3 Ambient Temperature... -
Page 5: Dc Characteristics
CS8952 DC CHARACTERISTICS (Over recommended operating conditions) Parameter Symbol Unit External Oscillator XTAL_I Input Low Voltage -0.3 XTAL_I Input High Voltage VDD+0.5 XTAL_I Input Low Current µA XTAL_I Input High Current µA XTAL_I Input Capacitance XTAL_I Input Cycle Time 39.996 40.004... - Page 6 CS8952 DC CHARACTERISTICS (CONTINUED) (Over recommended operating conditions) Parameter Symbol Unit Output High Voltage (MII_DRV = 0) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK = -4.0mA Input Low Voltage All Inputs Except AN[1:0], TCM, TXSLEW[1:0] Input High Voltage All Inputs Except AN[1:0], TCM, TXSLEW[1:0]...
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Page 7: 10Base-T Characteristics
CS8952 10BASE-T CHARACTERISTICS Parameter Symbol Unit 10BASE-T Interface Transmitter Differential Output Voltage (Peak) Receiver Normal Squelch Level (Peak) Receiver Low Squelch Level (LoRxSquelch bit set) 10BASE-T Transmitter TXD Pair Jitter into 100 Ω Load TTX1 TXD Pair Return to ≤50 mV after Last Positive µs... -
Page 8: 100Base-X Characteristics
CS8952 100BASE-X CHARACTERISTICS Parameter Symbol Unit 100BASE-TX Transmitter TX Differential Output Voltage (Peak) 0.95 1.05 Signal Amplitude Symmetry Signal Rise/Fall Time Rise/Fall Symmetry Duty Cycle Distortion +/-0.5 Overshoot/Undershoot Transmit Jitter 1400 TX Differential Output Impedance ohms 100BASE-TX Receiver Receive Signal Detect Assert Threshold Receive Signal Detect De-assert Threshold µs... -
Page 9: 100Base-Tx Mii Receive Timing - 4B/5B Aligned Modes
CS8952 100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES Parameter Symbol Unit RX_CLK Period RX_CLK Pulse Width RXD[3:0],RX_ER/RXD4,RX_DV setup to rising edge of RX_CLK RXD[3:0],RX_ER/RXD4,RX_DV hold from rising edge of RX_CLK CRS to RXD latency 4B Aligned 3 - 6... -
Page 10: 100Base-Tx Mii Receive Timing - 5B Bypass Align Mode
CS8952 100BASE-TX MII RECEIVE TIMING - 5B BYPASS ALIGN MODE Parameter Symbol Unit RX_CLK Period RX_CLK Pulse Width RXD[4:0] setup to rising edge of RX_CLK RXD[4:0] hold after rising edge of RX_CLK Start of 5B symbol to symbol output on RX[4:0]... -
Page 11: 100Base-Tx Mii Transmit Timing - 4B/5B Align Modes
CS8952 100BASE-TX MII TRANSMIT TIMING - 4B/5B ALIGN MODES Parameter Symbol Unit TXD[3:0] Setup to TX_CLK High TX_EN Setup to TX_CLK High TXD[3:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TX_EN Hold after TX_CLK High TX_EN “high” to CRS asserted latency CRS1 TX_EN “low”... -
Page 12: 100Base-Tx Mii Transmit Timing - 5B Bypass Align Mode
CS8952 100BASE-TX MII TRANSMIT TIMING - 5B BYPASS ALIGN MODE Parameter Symbol Unit TXD[4:0] Setup to TX_CLK High TXD[4:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TXD[4:0] Sampled to TX+/- output (TX Latency) TX_CLK Input/Output Data Input TXD[4:0]... -
Page 13: 10Base-T Mii Receive Timing
CS8952 10BASE-T MII RECEIVE TIMING Parameter Symbol Unit RX_CLK Period RX_CLK Pulse Width RXD[3:0], RX_ER, RX_DV setup to rising edge of RX_CLK RXD[3:0], RX_ER, RX_DV hold from rising edge of RX_CLK RX data valid from CRS RLAT RX+/- preamble to CRS asserted... -
Page 14: 10Base-T Mii Transmit Timing
CS8952 10BASE-T MII TRANSMIT TIMING Parameter Symbol Unit TXD[3:0] Setup to TX_CLK High TX_ER Setup to TX_CLK High TX_EN Setup to TX_CLK High TXD[3:0] Hold after TX_CLK High TX_ER Hold after TX_CLK High TX_EN Hold after TX_CLK High TX_EN “high” to CRS asserted latency CRS1 TX_EN “low”... -
Page 15: 10Base-T Serial Receive Timing
CS8952 10BASE-T SERIAL RECEIVE TIMING Parameter Symbol Unit RX+/- active to RXD[0] active 1200 DATA RX+/- active to CRS active RXD[0] setup from RX_CLK RXD[0] hold from RX_CLK RX_CLK hold after CRS off RXD[0] throughput delay CRS turn off delay... -
Page 16: 10Base-T Serial Transmit Timing
CS8952 10BASE-T SERIAL TRANSMIT TIMING Parameter Symbol Unit TX_EN Setup from TX_CLK EHCH TX_EN Hold after TX_CLK CHEL TXD[0] Setup from TX_CLK DSCH TXD[0] Hold after TX_CLK CHDU Transmit start-up delay STUD Transmit throughput delay TX_CLK Input/Output EHCH CHEL TX_EN... -
Page 17: Auto Negotiation / Fast Link Pulse Timing
CS8952 AUTO NEGOTIATION / FAST LINK PULSE TIMING Parameter Symbol Unit FLP burst to FLP burst FLP burst width FLPW Clock/Data pulses per burst Clock/Data pulse width µs Clock pulse to Data pulse 55.5 69.5 µs Clock pulse to clock pulse... -
Page 18: Serial Management Interface Timing
CS8952 SERIAL MANAGEMENT INTERFACE TIMING Parameter Symbol Unit MDC Period MDC Pulse Width MDIO Setup to MDC (MDIO as input) MDIO Hold after MDC (MDIO as input) MDC to MDIO valid (MDIO as output) DIRECTION: IN or OUT of chip... -
Page 19: Introduction
The CS8952 is a complete physical-layer transceiv- and decoupling, crystal and magnetics require- er for 100BASE-TX and 10BASE-T applications. ments, and twisted-pair and fiber transceiver con- Additionally, the CS8952 can be used with an ex- nections. ternal optical module for 100BASE-FX. 3. FUNCTIONAL DESCRIPTION... - Page 20 CS8952 VDD_MII 4.99 kΩ 25 MHz 0.1 µF 4.7 k Ω 4.7 k Ω 1.5 k Ω XTAL_I XTAL_O VSS18 VSS17 MDIO 49.9 Ω 49.9 Ω SHLD 51 Ω 75 Ω 51 Ω TX_ER/TXD[4] 51 Ω TX_EN 33 Ω TX_CLK 33 Ω...
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Page 21: Major Operating Modes
CS8952, eliminating the need 100BASE-X Don’t Repeater Care for the system to poll the CS8952 for state changes. The RX_EN signal allows the receiver outputs to 10BASE-T Serial Don’t Don’t be electrically isolated. The ISODEF pin controls... -
Page 22: Symbol Encoding And Decoding
CS8952 DATA and CONTROL Codes (RX_ER = 0 or TX_ER = 0) Name 5-bit Symbol 4-bit Nibble Comments 10100 0010 10101 0011 01010 0100 01011 0101 01110 0110 01111 0111 10010 1000 10011 1001 10110 1010 10111 1011 11010 1100... -
Page 23: 100 Mb/S Loopback
(address 18h). BP4B5B can be selected by set- Remote Function ting bit 14 of the same register. Loopback Loopback Pin BPALIGN causes more of the CS8952 to be (bit 9) (bit 8) No Loopback bypassed than the BP4B5B pin. BPALIGN also by- Local Loopback (toward MII) -
Page 24: 10Base-T Mii Application
1Ch), is set, the CS8952 automatically cor- 3.1.3.2 Collision Detection rects a reversal. If half duplex operation is selected, the CS8952 de- In the absence of transmit packets, the transmitter tects a 10BASE-T collision whenever the receiver generates link... -
Page 25: Carrier Detection
(address 18h) or mation and automatically configure both devices for maximum performance. When configured for asserting the LPBK pin. auto-negotiation, the CS8952 will detect and auto- 3.1.3.7 Carrier Detection matically operate full-duplex at 100 Mb/s if the de- vice on the other end of the link segment also... -
Page 26: Reset Operation
Auto-Neg Full 100 Mb/s modes. Table 5. After a reset, the CS8952 latches the signals on var- Auto-Negotiation encapsulates information within ious input pins in order to initialize key registers a burst of closely spaced Link Integrity Test Pulses, and goes through a self configuration. This in- referred to as a Fast Link Pulse (FLP) Burst. -
Page 27: Media Independent Interface (Mii)
CS8952 MII Frame Structure STATUS Pins COL - Collision indication, valid only for Data frames transmitted through the MII have the half duplex modes. following format: CRS - Carrier Sense indication Preamble Start of Data End of (7 Bytes) Frame... -
Page 28: Mii Receive Data
TX_ER must be synchronous with TX_CLK. This ing transferred across the MII. RX_ER will transi- will cause the CS8952 to replace the nibble with a tion synchronously with respect to the RX_CLK, HALT symbol in the frame being transmitted. This... -
Page 29: Mii Management Interface
PHY address 00000. The CS8952 de- ONE bits on MDIO with 32 corresponding clock termines its PHY address at power-up or reset cycles on MDC to provide the CS8952 with a pat- through the PHYAD[4:0] pins. tern that it can use to establish synchronization. -
Page 30: Configuration
The following pins are for dedicated control signals the MAC should tri-state the MDIO pin beginning and can be used at any time to configure the on the first bit time, and the CS8952 will begin CS8952. driving the MDIO signal to a logic ZERO during the second bit time. - Page 31 CS8952 Register Address Description Type PHY Identifier #1 Read-Only PHY Identifier #2 Read-Only Auto-Negotiation Advertisement Register Read/Write Auto-Negotiation Link Partner Ability Register Read-Only Auto-Negotiation Expansion Register Read-Only Auto-Negotiation Next Page Transmit Register Read/Write 8h through Fh Reserved by IEEE 802.3 Working Group...
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Page 32: Basic Mode Control Register - Address 00H
0 bit disables auto-negotiation. Power Down Read/Write 0 When this bit is set, the CS8952 enters a low power consumption state. Clearing this bit allows normal operation. Note: This bit is disabled, and writes to this bit are... - Page 33 CS8952 NAME TYPE RESET DESCRIPTION Restart Auto-Neg Read/Set Setting this bit causes auto-negotiation to be restarted. It is an Act-Once bit which is cleared once auto-negotiation has begun. Clearing this bit has no effect on the auto-negotiation process. Duplex Mode...
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Page 34: Basic Mode Status Register - Address 01H
The CS8952 does not support 100BASE-T4 opera- tion, so this bit will always read 0. 100BASE-TX/Full Read Only 1 When this bit is set, it indicates that the CS8952 is Duplex capable of 100BASE-TX Full-Duplex operation. This bit reflects the status of the 100BASE-TX/Full-Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). - Page 35 TYPE RESET DESCRIPTION Auto-Neg Ability Read Only 1 This bit indicates that the CS8952 has auto-negotia- tion capability. Therefore this bit will always read back a value of 1. Link Status Read Only 0 When set, this bit indicates that a valid link has been established.
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Page 36: Phy Identifier, Part 1 - Address 02H
CS8952 PHY Identifier, Part 1 - Address 02h Organizationally Unique Identifier: Bits[3:10] Organizationally Unique Identifier: Bits[11:18] NAME TYPE RESET DESCRIPTION 15:0 Organizationally Read/Write 001Ah This identifier is assigned to PHY manufacturers by Unique Identifier the IEEE. Its intention is to provide sufficient informa-... -
Page 37: Phy Identifier, Part 2 - Address 03H
Part Number Read/Write 10 0000 These bits indicate the CS8952 part number. It has been set to a value of 100000. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. -
Page 38: Auto-Negotiation Advertisement Register - Address 04H
12:5 Technology Ability Read/Write 0000 1111 This field determines the advertised capabilities of Field the CS8952 as shown below. When the bit is set, the corresponding technology will be advertised during auto-negotiation. BIT Capability Reserved Reserved PAUSE operation for full duplex links. -
Page 39: Auto-Negotiation Link Partner Ability Register - Address 05H
Next Page exchange. Acknowledge Read Only 0 When set, this bit indicates that the link partner has received consistent data from the CS8952. Remote Fault Read Only 0 This bit indicates that a fault condition occurred on the far end. -
Page 40: Auto-Negotiation Expansion Register - Address 06H
Next Page Able Read Only 1 This bit is a status bit which indicates to the Manage- ment Layer that the CS8952 supports Next Page capability. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. -
Page 41: Auto-Negotiation Next-Page Transmit Register - Address 07H
Read/Write 0 When set, this bit indicates to the link partner that the CS8952 can comply with the last received message. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. -
Page 42: Interrupt Mask Register - Address 10H
Link Status Change Read Write 1 When set, an interrupt will be generated each time the CS8952 detects a change in the link status. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. - Page 43 CS8952 NAME TYPE RESET DESCRIPTION DCR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in the DCR counter becomes set. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
- Page 44 CS8952 NAME TYPE RESET DESCRIPTION Auto-Neg Complete Read/Write 0 When set, an interrupt will be generated once auto- negotiation has completed successfully. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.
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Page 45: Interrupt Status Register - Address 11H
CS8952 6.10 Interrupt Status Register - Address 11h Remote CIM Link Link Status Descrambler Premature End FCCR RECR Loopback Unstable Change Lock Change Error Rollover Rollover Rollover Fault Reset Jabber Auto-Neg Parallel Parallel Remote Page Reserved Complete Detect Complete Detection Fault... - Page 46 CS8952 NAME TYPE RESET DESCRIPTION Remote Loopback Read Only 0 When set, this bit indicates that the Elastic Buffer has Fault detected an over-run or an under-run condition. In any case, the frame generating this fault will be ter- minated.
- Page 47 CS8952 NAME TYPE RESET DESCRIPTION Remote Fault Read Only 0 When auto-negotiation is enabled, this bit is set if the Remote Fault bit is set in the Auto-Negotiation Link Partner Ability Register (address 05h). When auto- negotiation is disabled, this bit will be set when the Far-End Fault Indication for 100BASE-TX is detected.
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Page 48: Disconnect Count Register - Address 12H
DESCRIPTION 15:0 Disconnect Counter Read/Write 0000h This field contains a count of the number of times the CS8952 has lost a Link OK condition. This counter is cleared upon readout and will roll-over to 0000h. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver... -
Page 49: False Carrier Count Register - Address 13H
Read Only 0000h This field contains a count of the number of times the Counter CS8952 has detected a false-carrier -- that is, the reception of a poorly formed Start-of-Stream Delim- iter (SSD). The counter is incremented at the end of such events to prevent multiple increments. -
Page 50: Scrambler Key Initialization Register - Address 14H
CS8952 6.13 Scrambler Key Initialization Register - Address 14h Load Reserved Scrambler Initialization Key Scrambler Initialization Key NAME TYPE RESET DESCRIPTION Load Read/Set When this bit is set, the scrambler will be loaded with the value in the Scrambler Initialization Key field. -
Page 51: Receive Error Count Register - Address 15H
CS8952 6.14 Receive Error Count Register - Address 15h Receive Error Counter Receive Error Counter NAME TYPE RESET DESCRIPTION 15:0 Receive Error Read Only 0000h This counter increments for each packet in which one Counter or more receive errors is detected that is not due to a collision event. -
Page 52: Descrambler Key Initialization Register - Address 16H
CS8952 6.15 Descrambler Key Initialization Register - Address 16h Load Reserved Descrambler Initialization Key Descrambler Initialization Key NAME TYPE RESET DESCRIPTION Load Read/Set When this bit is set, the descrambler will be loaded with the value in the Descrambler Initialization Key field. -
Page 53: Pcs Sub-Layer Configuration Register - Address 17H
CS8952 6.16 PCS Sub-Layer Configuration Register - Address 17h Time-Out Time-Out Repeater MR Preamble NRZI Enable LED5 Mode Unlock Regs Fast Test Select Disable Mode Enable CLK25 Disable Enable LT/100 CIM Disable Tx Disable Rx Disable LED1 Mode LED4 Mode... - Page 54 CS8952 NAME TYPE RESET DESCRIPTION MF Preamble Read/Write 0 When set, this bit will force all management frames Enable (via MDIO, MDC) to be preceded by a 32 bit pream- ble pattern of contiguous ones to be considered valid. When cleared, it allows management frames with or without the preamble pattern.
- Page 55 CS8952 NAME TYPE RESET DESCRIPTION Rx Disable Read/Write 0 When set, the receiver is disabled and no incoming packets pass through the receiver. The link will remain established and, if operating at 100 Mb/s, the descrambler will remain locked. When clear, the receiver is enabled.
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Page 56: Loopback, Bypass, And Receiver Error Mask Register - Address 18H
If the 4B5B encoders are being bypassed, this event will be reported by setting RX_DV=0 and RXD[4:0]=11110. If symbol alignment is bypassed, the CS8952 does not detect carrier, and thus will not report bad SSD events. Bypass 4B5B Read/Write Reset to the value... - Page 57 The loopback includes all of the 100BASE-TX functionality except for the MLT-3 encoding/decoding and the analog line-interface blocks. When clear, the CS8952 is configured for normal operation. Note: Setting Remote Loopback and PMD Loopback simultaneously will cause neither loopback mode to be entered, and should not be done.
- Page 58 CS8952 NAME TYPE RESET DESCRIPTION Link Error Report Read/Write 0 When set, this bit causes link errors to be reported by Enable a value of 3h on RXD[3:0] and the assertion of RX_ER. When clear, link errors are not reported across the MII.
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Page 59: Self Status Register - Address 19H
This bit may be used to determine the current status of the link. Power Down Read Only 1 When high, this bit indicates that the CS8952 is in a low power state. Receiving Data Read Only 0 This bit is high whenever the CS8952 is receiving valid data. - Page 60 These bits define the PHY PHYAD[4:0] pins. address used by the management layer to address the PHY. The external logic must know this address in order to select this particular CS8952’s registers individually via the MDIO and MDC pins. CrystalLAN™ 100BASE-X and 10BASE-T Transceiver...
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Page 61: 10Base-T Status Register - Address 1Bh
When set, this bit selects 10BASE-T serial mode. on the 10BT_SER When low, this bit selects 10BASE-T nibble mode. pin. This bit will only affect the CS8952 if it has been con- figured for 10 Mb/s operation. Reserved Read Only 0 0000 0000... -
Page 62: 10Base-T Configuration Register - Address 1Ch
If link pulses are disabled during 100 Mb/s operation with auto-negotiation enabled, the CS8952 will go into 10 Mb/s mode. If operating in 100 Mb/s mode with no auto-negotiation, then clear- ing this bit has no effect. -
Page 63: Design Considerations
DESCRIPTION Jabber Enable Read/Write 1 When set, the jabber function is enabled. When clear, and if the CS8952 is in 10BASE-T full-duplex or 10BASE-T ENDEC loopback mode, the jabber function is disabled. Note: When the National Compatibility Mode bit (bit... -
Page 64: 100Base-Fx Interface
Figure 7. Recommended Connection of Fiber Port TX_NRZ+/- termination components should be tor biases the internal analog circuits of the CS8952 placed as close to the fiber transceiver as possible, and should be placed as close as possible to RES while RX_NRZ+/- and SIGNAL+/- termination pin. -
Page 65: Recommended Magnetics
CS8952 Power Supply and Decoupling 4.99 k Ω The CS8952 supports connection to either a 3.3 V Via to Ground Plane or 5.0 V MII. When connected to a +5.0 V MII, all power pins should be provided +5.0 V +/- 5%, and... -
Page 66: General Layout Recommendations
(pins 76-100) of CS8952. Place • Depending on the orientation and location of the CS8952 in turn as close to T1 as possible. the transformer, the CS8952, and the RJ-45, • Use the bottom layer for signal routing as a sec- and on whether the application is for a NIC or a ond choice. - Page 67 CS8952. secondary (network) side and the RJ-45. How- • Locate the crystal as close to the CS8952 as ever, a chassis plane may be added in this re- possible, running short traces on the component gion to pick up the metal tabs of a shielded RJ- side in order to reduce parasitic load capaci- 45.
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Page 68: Pin Descriptions
Pin Diagram RSVD RSVD LED5 TX_NRZ- LED4 TX_NRZ+ LED3 RX_NRZ- LED2 RX_NRZ+ LED1 SIGNAL- SPD10 SIGNAL+ SPD100 VDD_MII CS8952 100-pin PWRDN TQFP ISODEF RX_EN (14 mm x 14 mm) BPSCR RESET TXSLEW1 REPEATER TXSLEW0 CLK25 BP4B5B VDD_MII 10BT_SER TEST0 BPALIGN... - Page 69 MDIO - Management Data Input/Output. Bi-Directional, Pin 27. Bi-directional signal used to transfer management data between the CS8952 and the Ethernet controller. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the MDIO pin should have an external 1.5 KΩ...
- Page 70 CS8952 In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RX_CLK pin should have an external 33 Ω series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistor may not be necessary.
- Page 71 TX_CLK - Transmit Clock. Input/Tri-State Output, Pin 42. Continuous clock signal used by the CS8952 as a reference clock to sample TXD[3:0], TX_ER, and TX_EN. TX_CLK can be referenced either internally (Output Mode) or externally (Input Mode) based upon the value of the TCM pin at power-up or at reset.
- Page 72 TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38. When high, TX_ER indicates to the CS8952 that a transmit error has occurred. If TX_ER is asserted simultaneously with TX_EN in 100 Mb/s mode, the CS8952 will ignore the data on the TXD[3:0] pins and transmit one or more 100 Mb/s HALT symbols in its place.
- Page 73 CS8952 AN1 pin AN0 pin Speed Forced/Auto Full/Half Duplex 10 Mb/s Forced Full 100 Mb/s Forced Half 100 Mb/s Forced Full 100/10 Mb/s Auto-Neg Full/Half 10 Mb/s Auto-Neg Half 10 Mb/s Auto-Neg Full 100 Mb/s Auto-Neg Half 100 Mb/s Auto-Neg...
- Page 74 CS8952 BP4B5B - Bypass 4B5B Coders. Input, Pin 56. When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B decoder are bypassed. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The 4B5B Coders may also be bypassed under software control through bit 14 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h).
- Page 75 LPBK - Loopback Enable. Input, Pin 51. When this pin is asserted high and the CS8952 is operating in 100 Mb/s mode, the CS8952 will perform a local loopback inside the PMD block, routing the scrambled NRZI output to the NRZI input port on the descrambler.
- Page 76 When this active-low input is asserted during power-up or reset, the CS8952 will exit reset in a low power configuration, where the only circuitry enabled is that necessary to maintain the media impedance. The CS8952 will remain in a low power state until RESET pin is asserted or the MDC pin toggles.
- Page 77 4.7 KΩ pull-up or pull-down resistor. SPD10 - 10 Mb/s Speed Indication. Output, Pin 68. This pin is asserted high when the CS8952 is configured for 10 Mb/s operation. This pin can be used to drive a low-current LED to indicate 10 Mb/s operation.
- Page 78 CLK25 - 25 MHz Clock. Output, Pin 17. A 25 MHz Clock is output on this pin when the CS8952 is configured to use an external reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating modes.
- Page 79 CS8952 RESET - Reset. Input, Pin 15. This active high input initializes the CS8952, and causes the CS8952 to latch the input signal on the following pins: COL/PHYAD0, CRS/PHYAD2, RX_ER/PHYAD4/RXD4, 10BT_SER, BP4B5B, BPALIGN, BPSCR, ISODEF, REPEATER, RXD[1]/PHYAD1, and RXD[3]/PHYAD3. XTAL_I - Crystal Input, Pin 96.
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Page 80: Package Dimensions
CS8952 PACKAGE DIMENSIONS 100L TQFP PACKAGE DRAWING ∝ INCHES MILLIMETERS 0.063 1.60 0.002 0.006 0.05 0.15 0.007 0.011 0.17 0.27 0.618 0.642 15.70 16.30 0.547 0.555 13.90 14.10 0.618 0.642 15.70 16.30 0.547 0.555 13.90 14.10 0.016 0.024 0.40 0.60 0.018... - Page 81 • Notes •...
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