Tap/Itp Checklist For 370-Pin Socket Processors; Tap/Itp Signals - Intel Pentium III Design Manual

Table 8-2. CMOS Signals (Sheet 2 of 2)
CPU Pin
LINT1/NMI
PICD[1:0]
PWRGOOD
SLP#
SMI#
STPCLK#
THERMTRIP#
8.5

TAP/ITP Checklist for 370-Pin Socket Processors

There are several mechanical, electrical, and functional constraints on the debug port which must be
followed, please see the Intel
Chapter 3 of this document for details.
Table 8-3. TAP/ITP Signals
CPU Pin
PRDY#
PREQ#
TCK
TDO
TDI
TMS
TRST#
® ®
Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
Connect to interrupt control logic and second CPU and pull up through ~330 Ω to
VccCMOS. For boards supporting preproduction processors, this pin must be
connected to frequency selection circuitry.
Connect to second CPU and pull up through ~150 Ω to VccCMOS. May also
need to be connect to interrupt control logic.
Connect to second CPUs and pull up through 150-330 Ω to 1.8 V. output from the
PWRGOOD logic.
Connect to second CPU and pull up through ~330 Ω to Vcc
need to be connected to chipset or compatibility logic.
Connect to second CPU and pull up through ~330 Ω to Vcc
need to be connected to chipset or compatibility logic.
Connect to second CPU and pull up through ~330 Ω to Vcc
need to be connected to chipset or compatibility logic.
See Chapter 6 for more information.
® ®
Pentium III Processor with 512KB L2 Cache Datasheet, along with
Pull-up resistor that matches GTL characteristic impedance to VTT, 240 Ω series
resistor to ITP.
200-300 Ω pull-up to VccCMOS and connect to ITP.
39 Ω pull-down to Gnd, and connect to ITP.
150 Ω pull-up to VccCMOS and connect to ITP.
200-300 Ω pull-up to VccCMOS and connect to ITP.
Connect TDI from CPU0 to TDO on CPU1.
39 Ω pull-up to VccCMOS and connect to ITP.
500-680 Ω pull-down to Gnd and connect to ITP.
Pin Connection
CMOS1.5
CMOS1.5
CMOS1.5
Pin Connection
. May also
. May also
. May also
8-3