Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 35

X-Ref Target - Figure 1-28
12. The SuperClock-2 source code now needs to be added to the example ibert wrapper.
VC7203 IBERT Getting Started Guide
UG847 (v3.0) July 10, 2013
Figure 1-28: Sources after Running add_scm2.tcl
Double-click example_ibert_7series_gtx_0 in the Design Sources to open the verilog
code. Add the top level ports from top_scm2.v to the module declaration and
instantiate the top_scm2 module in the example ibert wrapper
File > Save File.
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Creating the GTX IBERT Core
(Figure 1-29). Click
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