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Xilinx Virtex-7 FPGA VC7203 Getting Started Manual page 8

Characterization kit ibert
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Chapter 1: VC7203 IBERT Getting Started Guide
X-Ref Target - Figure 1-1
All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with Samtec BullsEye connectors.
pad.
8
Figure 1-1: GTX Quad Locations
Figure 1-2
B shows the connector pinout.
www.xilinx.com
QUAD_118
QUAD_119
Figure 1-2
A shows the connector
VC7203 IBERT Getting Started Guide
UG847 (v3.0) July 10, 2013
UG847_c1_01_1026112

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