Sony PCS-1500 Service Manual page 119

[AC block]
The AC block consists of the combination of Audio Codec DSP (IC520) and the 256 kbit-SRAM
(IC521), the combination of the Audio Codec DSP (IC530) and the 256 kbit-SRAM (IC531), VCO/PLL
(IC500) and the Serial Timing Generator (IC501).
from/to
CPU BLOCK
\HCS_AC1
LVHA1,2
2
\LVHRD
\LVHWR_P
LVHD0-7
8
\RES_AC
from X510
7.5MHz
The Audio Codec DSPs (IC520, IC530) have the function of compression/decompression, decoding/
coding of the audio data and generation of ringer tone. The 256-kbit SRAMs (IC521, IC531) are used as
the data processing buffer of the DSPs. The program code that is required to operate the DSPs is partly
downloaded from the CPU and stored in the RAM inside the DSP. (A part of the program code has been
masked in DSP.) The operating clock (7.5 MHz) of the DSP is supplied from the crystal oscillator X510.
Resetting is performed by the "RES_AC" signal that is supplied from the CPU block. (Refer to Fig. 3-16.)
Inputting and outputting of the audio signal to and from the DSPs (IC520, IC530) are performed in the
form of a serial signal. Connection of the serial signal is shown in Fig. 3-17. The serial signal of the EC
block side performs receiving the before-compressed/coded (transmission) audio data from the Echo
Canceller DSP (IC570) and transmission of the decompressed/decoded (receiving) audio data and the
other audio data such as ringer tone, etc., to the Echo Canceller DSP (IC570). The serial signal of the
VCP block side performs transmission of the compressed/coded (transmission) audio data to the VCPex
(IC300) and receiving the before decompressed/decoded (receiving) audio data from the VCPex (IC350).
The clock signal and the frame sync signals for the serial signals are generated by the Serial Timing
Generator (IC501). The frame sync signals that connect the AC block and the EC block are synchronized
with the line's 8 kHz rate. The frame sync signals that connect the AC block and the VCP block are
synchronized with the trigger signal which is output from VCPex (IC300).
The Serial Timing Generator (IC501) generates the serial timing signals that are used in between the AD/
DA-converter (IC600) and Echo Canceller DSP (IC570), the 8 kHz clock that is used by the internal
processing of the Audio Codec DSPs (IC520, IC530), and the 16 kHz clock that is used by the internal
processing of the Echo Canceller DSPs (IC570, IC540).
The VCO/PLL (IC500) generates the 8.192 MHz clock that is phase-locked by the PLL to the 8 kHz
clock ("LV_NET8K") which is synchronized with the line signal. The 8.192 MHz clock is sent to the
Serial Timing Generator (IC501). The VCO/PLL (IC500) is controlled by the "SLP_STB" signal so that
it stops oscillation during the sleep mode.
It operates on the +3.3 V-2 power supply voltage.
PCS-1500/1500P
Audio Codec1(IC520)
uPD77019GC-017
\HCS
HA ,HA
0 1
\HRD
\HWR
HD -HD
0 7
\RESET
X1
256Kbit SRAM(IC521)
32Kx8bit
Fig. 3-16 Host Interface of AC Block
Audio Codec2(IC530)
uPD77019GC-017
from/to
CPU BLOCK
\HCS_AC2 \HCS
LVHA1,2 HA ,HA
0 1
2
\LVHRD \HRD
\LVHWR_P \HWR
LVHD0-7 HD -HD
0 7
8
\RES_AC \RESET
from X510
7.5MHz X1
256Kbit SRAM(IC531)
3-2. Circuit Description of the Respective Boards
32Kx8bit
3-29