Sony PCS-1500 Service Manual page 116

3-2. Circuit Description of the Respective Boards
[VIDAD block]
The VIDAD block performs a part of the input video signal selection, A/D conversion, converting the
signal to the Rec.601 format and pre-filter processing to help video compression.
Fig. 3-15 shows connection with the analog video signal, system bus and the Video Decoder (IC400).
As the power to the video input analog circuit, the +5 V-3 power that is generated from the +5 V-2
power after passing through an LC filter is used.
The respective input video signals are input to the following terminal of the Video Decoder (IC400).
Camera
AUX-1 connector
AUX-2 connector
AV-Link (DE-54 board) : To the "NTSC/PAL2" terminal
Selection of the S-Video (YC) input signal from either camera or to AUX-1, is performed by the Video
Selector (IC401) of the VIDIN block. When the input signal is introduced to the Video Decoder (IC400),
the common terminal is used as the input terminal. Selection of a terminal among the "NTSC/PAL1" to
"NTSC/PAL3" terminals is performed inside the Video Decoder (IC400). The video signal that is
selected inside the Video Decoder (IC400) is output once from the "YOUT" terminal and input to the
"YIN" terminal after passing through the phi type filter. The chrominance signal that is input to the "C"
terminal is used only when the "NTSC/PAL3" terminal is used.
Setup of the Video Decoder (IC400) is performed by the CPU using the I
nals) via the Graphics Overlay ASIC (IC352). The Video Decoder (IC400) is reset by the output port of
the Graphics Overlay ASIC (IC352) or by setting the register inside the Video Decoder (IC400). At the
same time, the Video Decoder (IC400) can output the interrupt signal "IRQ_VDEC".
The operating clock signal (27 MHz) of the Video Decoder (IC400) is created by buffering the output of
the Graphics Overlay ASIC (IC352) with IC354 and IC405.
The pre-filter processing of the input video signal is performed by the Pre-filter ASIC (IC350). The Pre-
filter ASIC (IC350) applies the inter-frame filtering processing to the video signal that is output from the
Video Decoder (IC400) with the Field Memory (IC351). (Refer to Fig. 3-14.)
The video data that is input to the Pre-filter ASIC (IC350) from the Video Decoder (IC400) is the 8-bit
data in which the luminance and the chrominance signals are multiplexed. The F/F (IC356 to IC358) is
inserted into the field ID signal and the video data among the video signals that are input to the Pre-filter
ASIC (IC350), for timing adjustment.
Pre-filter ASIC (IC350) filter ON/OFF and the degree of filtering are set by the output "AUX0 to AUX3"
of VCPex (IC300). (Refer to the table 1.)
VCPex AUX-Port
AUX0
AUX1
AUX2
AUX3
AUX4
The operating clock signal (27 MHz) is created by buffering the output of the Graphics Overlay ASIC
(IC352) with IC354. Reset is controlled by the output port of the Graphics Overlay ASIC (IC352).
(Refer to Fig. 3-15.)
It operates on the +3.3 V-2 and the +5 V-2 power supply voltage.
3-26
: Luminance signal is input to the "NTSC/PAL3" terminal via IC401
Chrominance signal is input to the "C" terminal via IC401
: Luminance signal is input to the "NTSC/PAL3" terminal via IC401
Chrominance signal is input to the "C" terminal via IC401
: To the "NTSC/PAL1" terminal via Q406
Table 1
Dir.
Out Setting Parameter of Pre-filter ASIC
Out Setting Parameter of Pre-filter ASIC
Out Setting Parameter of Pre-filter ASIC
Out Setting Bypass-mode of Pre-filter ASIC
In Getting Field-ID of Screen-Video-Output
2
C bus ("SCL", "SDA" termi-
Function
PCS-1500/1500P