Sony PCS-1500 Service Manual page 111

3-2. Circuit Description of the Respective Boards
[NETIF block]
Fig. 3-12 shows connection of the NETIF block.
The NETIF block converts the array of the line data that is sent and received between both the BRI block
and the optional board and the VCP block, into the format that suits the respective blocks. It also per-
forms switching of the optional board interfaces in accordance with the optional board in use.
Converting the data array means to convert the multiple pairs (a pair of send/receive data for each
BRI-1B) of the serial data that is input and output to and from the BRI block or the optional boards, to a
pair of send/receive serial data that is input and output to and from the VCP block. When the V.35
interface is used, the serial data whose clock changes continuously in accordance with the communication
speed of the communication line in use, is converted to the serial data that has the stable clock frequency
(3.072 MHz) of the VCP block circuit and is not continuous in every 8 kHz frame. The reverse conver-
sion is also included. These conversion operations are performed inside the TDM_ASIC (IC750).
In addition to the above-described operations, the TDM_ASIC (IC750) performs the following opera-
tions: generation of the 8 kHz clock that is synchronized with the line and is supplied to the AC block;
generation of the 12.288 MHz clock that is used as the operating clock of the BRI block and the IF-744
board; and detection of the line speed (including generation of interrupt when the line speed changes) for
the V.35 interface. The TDM_ASIC (IC750) is partly used for the input/output port that controls and
detects the respective blocks of SIRCS, BRI, AUANA and PWR.
The operating clock signal (12.288 MHz) of the TDM_ASIC (IC750) is generated by the crystal oscillator
(X750).
The interfaces for the optional boards are switched depending upon whether the connected optional board
is the IF-744 board (BRI-4B)/IF-745 board (V.35) or the IF-761 board (10BASE-T). Selection of the
optional board interfaces is performed by controlling the buffers (IC751 to IC753, IC755, IC756) using
the "LAN_EN" signal that is supplied from the optional board. In order to secure the data bus width 16
bits when interfaced with the IF-761 board (while interfacing with other boards uses 8 bits), the 8 signal
lines that are used to send/receive the line data when interfacing with the IF-744 board, can be switched to
be used as the higher order 8 bits of a data bus.
The interrupt signals from the optional boards also are output to the CPU block as different signals
depending on whether the IF-761 board is connected or not (switching by IC752 and IC756). At the same
time, the "WAIT_OP" signal that is the wait request for the CPU bus cycle can be output to the CPU
block when the IF-761 board is connected.
The NETIF block is reset by the "RES_ALL" signal that is supplied from the CPU block.
It operates on the +5 V power supply voltage.
3-21
PCS-1500/1500P