Sony PCS-1500 Service Manual page 110

3-2. Circuit Description of the Respective Boards
Host Bus Decoder Block
(IC804,803,807,812)
from
CPU BLOCK
\HCS_BRI
HA4,5
2
\MODESET
\DOWNLOAD
from
NETIF BLOCK(IC750)
\SDETCLR
from
CPU BLOCK
DIR
\HDEN
MODE_SET
from
NETIF BLOCK(IC750)
from/to
CPU BLOCK
HA1-3
\HRD
\HWR
HD0-7
from
NETIF BLOCK(IC750)
CK12M
from
CPU BLOCK
\RES_BRI
3-20
CLK_L,H
\OE
\DOE
\RAM
\81504
\STAT
to/from
NETIF BLOCK
(IC750)
Fig. 3-11 BRI Block
Latch(IC808,809)
D Q
8 15
CLK
2
\OC
Buffer(IC811)
\G
Transceiver(IC810)
8 8
DIR
\OE
I-Interface Controller(IC800)
HD81504RFE
TEST0
\CS \ROMCS
OAD \RAMCS
2-0
3
\ORD A
14-0
15
\OWE \RD
OD \WR
7-0
8
D
7-0
8
EXTAL
\WDT
\RESET
CK8K
CK64K
T202
RBA LRA
RBB LRB
T201
TBA LTA
TBB LTB
256Kbit SRAM(IC801)
\CE
A
0-14
\OE
\WE
I/O
0-7
256Kbit SRAM(IC802)
\CE
A
0-13
\OE
\WE
I/O
0-7
Status Latch Block
to
(IC806,805,803)
NETIF BLOCK
(IC750)
\INT \INT_BRI
Buffer(IC758)
A
12,13
HD0
SDET
HD2
CHK
HD4
NTSC/PAL
HD7
from CN910
\CAM_LOCK
\G
FL800
from CN800
to CN800
PCS-1500/1500P