Sony PCS-1500 Service Manual page 106

3-2. Circuit Description of the Respective Boards
[PCMCIA block]
The most of signals that are required by the PCMCIA interface can be obtained from the CPU bus signal.
Connections of the CPU bus and buffer are shown in Fig. 3-6. The signals that cannot be obtained by the
CPU bus are connected as follows.
A25, REQ/REG:
Output port of IC202 (UART of UART block) is connected via IC132 (buffer).
RESET:
Output of IC110 (Bus control PLD) is connected via IC132 (buffer).
CD1, CD2:
These are input to the PCM power supply control circuit. "CD1&CD2" is input to the CPU bus
via IC134 (buffer).
RDY/BSY or IREQ, WP or IOCS16, RFU/INPACK, BVD2 or SPKR, BVD2 or STSCHG :
These are input to the CPU bus via IC134 (buffer).
RDY/BSY or IREQ, WAIT:
These are connected to IC110 (bus control PLD of CPU block) via IC133 (buffer).
At the same time, the interrupts that come from PCMCIA can be masked by the bus control PLD (IC110)
of the CPU block.
Power Control Circuit(IC137-139)
\VS1
\VS2
from PCMCIA I/F
\CD1
\CD2
from IC110 PWR_PCM
to IC134,IC110
to IC134
to IC131-133
Fig. 3-8 shows the power supply control block for the PCMCIA interface. VPP and VCC of the
PCMCIA are switched by controlling the switch IC (IC135) in accordance with the card being used
(detected by the VS1 and VS2 signals.) However, VPP is fixed to +5 V. Both VCC and VPP are turned
on only when the card is detected (both CD1 and CD2 signals are connected to GND) and the PWR_PCM
signal coming from IC110 is high.
The buffer operates on the +3.3 V-2 power, and the card detection and power supply control circuit
operate on the +3.3 V. The power that is supplied to the card is either +5 V or +3.3 V.
3-16
+3.3V +5V
Vcc=3.3V
!(!\CD1 & !\CD2
& PWR_PCM)
!\CD1 & !\CD2
2
2
Fig. 3-8 Power Ccontrol of PCMCIA Block
PCMCIA Power Interface Switch(IC135)
TPS2211
+12V
12V AVPP
5V
3.3V AVCC
VPPD0-1
\VCCD0-1 \OC
to "VPP" of PCMCIA
to "VCC" of PCMCIA
PCS-1500/1500P