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CP321
4.3.6
Watchdog Control Register
The Watchdog Control register is the interface between applications and the operating system
for controlling the functioning of the Watchdog. Together with the Event Register, bit 0 (WD)
and bit 2 (PB2), the possibility is provided for either hardware (Abort switch) or software
(Watchdog timer) intervention in the execution of the application.
Table 4-9: Watchdog Control Register
REGISTER NAME
ADDRESS
BIT POSITION
CONTENT
WD_EN
DEFAULT
BIT
NAME
0
WDT0
1
WDT1
2
3
4
WD_TRG
5
WD_CCD
6
WD_R
7
WD_EN
ID 24977, Rev. 02
WATCHDOG CONTROL
0xFFE0 0018
7
6
5
WD_R
res.
0
0
n/a
VAL
0
Settings: WDT1 WDT0
0
1
0
0
1
1
1
0
reserved
1
0
reserved
1
When WD-EN (bit 7) set to 1, indicates that Watchdog timer has not been retrig-
0
gered.
Causes the Watchdog to be retriggered
1
(Resets Watchdog timer to value indicated by bits 0 and 1, and WD_TRG (bit 4)
to 0)
Normal watchdog functionality
0
Cascade mode: when watchdog timout occurs, an NMI will be generated, the
1
watchdog timer resets, a further timeout will result in a system reset (when
WD_R is first set to 1)
0
Causes hardware reset of system upon Watchdog timeout
1
Causes generation of a non-maskable interrupt upon Watchdog timeout
0
Watchdog timer disabled
Watchdog timer enabled
Note...
1
Once the Watchdog timer is enabled it
cannot be disable except by resetting the
system.
© 2003 Kontron Modular Computers GmbH
4
3
res.
WD_TRG
0
n/a
DESCRIPTION
0
0.5 seconds Watchdog timeout time
1
1.0 seconds Watchdog timeout time
0
1.5 seconds Watchdog timeout time
1
2.0 seconds Watchdog timeout time
Configuration
ACCESS
R
W
2
1
0
res.
WDT1
WDT0
n/a
n/a
n/a
Page 4 - 11
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