Quectel EC25-AUX Hardware Design page 64

Table 19: Pin Definition of SGMII Interface
Pin Name Pin No.
Control Signal Part
EPHY_RST_N 119
EPHY_INT_N 120
SGMII_MDATA 121
SGMII_MCLK 122
USIM2_VDD 128
SGMII Signal Part
SGMII_TX_M 123
SGMII_TX_P 124
SGMII_RX_P 125
SGMII_RX_M 126
The following figure shows the simplified block diagram for Ethernet application.
Figure 27: Simplified Block Diagram for Ethernet Application
The following figure shows a reference design of SGMII interface with PHY AR8033 application.
EC25_Hardware_Design
I/O Description
DO Ethernet PHY reset
DI Ethernet PHY interrupt
SGMII MDIO (Management Data
IO
Input/Output) data
SGMII MDIO (Management Data
DO
Input/Output) clock
PO SGMII MDIO pull-up power source
AO SGMII transmission - minus
AO SGMII transmission - plus
AI SGMII receiving - plus
AI SGMII receiving - minus
LTE Standard Module Series
EC25 Hardware Design
Comment
1.8V/2.85V power domain
1.8V power domain
1.8V/2.85V power domain
1.8V/2.85V power domain
Configurable power source.
1.8V/2.85V power domain.
External pull-up power source for
SGMII MDIO pins.
Connect with a 0.1uF capacitor,
and is close to the PHY side.
Connect with a 0.1uF capacitor,
and is close to EC25 module.
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