Quectel EC25-AUX Hardware Design page 29

DBG_TXD 12
DBG_RXD 11
ADC Interfaces
Pin Name Pin No.
ADC0 45
ADC1 44
1)
PCM Interface
Pin Name Pin No.
PCM_IN 24
PCM_OUT 25
PCM_SYNC 26
PCM_CLK 27
I2C Interface
EC25_Hardware_Design
DO Transmit data
DI Receive data
I/O Description
General purpose
AI analog to digital
converter
General purpose
AI analog to digital
converter
I/O Description
DI PCM data input
DO PCM data output
PCM data frame
IO synchronization
signal
IO PCM clock
LTE Standard Module Series
EC25 Hardware Design
V max=0.45V
OL
V min=1.35V
OH
V min=-0.3V
IL
V max=0.6V
IL
V min=1.2V
IH
V max=2.0V
IH
DC Characteristics
Voltage range:
0.3V to VBAT_BB
Voltage range:
0.3V to VBAT_BB
DC Characteristics
V min=-0.3V
IL
V max=0.6V
IL
V min=1.2V
IH
V max=2.0V
IH
V max=0.45V
OL
V min=1.35V
OH
V max=0.45V
OL
V min=1.35V
OH
V min=-0.3V
IL
V max=0.6V
IL
V min=1.2V
IH
V max=2.0V
IH
V max=0.45V
OL
V min=1.35V
OH
V min=-0.3V
IL
V max=0.6V
IL
V min=1.2V
IH
V max=2.0V
IH
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
Comment
If unused, keep it
open.
If unused, keep it
open.
Comment
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
In master mode, it is
an output signal.
In slave mode, it is an
input signal.
If unused, keep it
open.
1.8V power domain.
In master mode, it is
an output signal.
In slave mode, it is an
input signal.
If unused, keep it
open.
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