Quectel EC25-AUX Hardware Design page 56

The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 14: Pin Definition of PCM and I2C Interfaces
Pin Name Pin No.
PCM_IN 24
PCM_OUT 25
PCM_SYNC 26
PCM_CLK 27
I2C_SCL 41
I2C_SDA 42
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC. Please refer to
document [2] for more details about AT+QDAI command.
The following figure shows a reference design of PCM interface with external codec IC.
EC25_Hardware_Design
Figure 23: Auxiliary Mode Timing
I/O Description
DI PCM data input
DO PCM data output
PCM data frame
IO
synchronization signal
IO PCM data bit clock
OD I2C serial clock
OD I2C serial data
LTE Standard Module Series
EC25 Hardware Design
Comment
1.8V power domain
1.8V power domain
1.8V power domain
1.8V power domain
Require external pull-up to 1.8V
Require external pull-up to 1.8V
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