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Quectel EC25-AUX Hardware Design page 31

Lte standard module series
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SDC2_
30
DATA1
SDC2_
31
DATA0
SDC2_CLK
32
SDC2_CMD
33
EC25_Hardware_Design
SD card SDIO bus
IO
DATA1
SD card SDIO bus
IO
DATA0
SD card SDIO bus
DO
clock
SD card SDIO bus
IO
command
LTE Standard Module Series
EC25 Hardware Design
V
max=3.34V
IH
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
V
max=0.38V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
V
max=0.38V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
3.0V signaling:
V
max=0.38V
OL
V
min=2.01V
OH
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
IL
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
SDIO signal level can
be selected according
to SD card supported
level, please refer to
30 / 130
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