Ams Demonstration - Xilinx AMS101 User Manual

Chapter 4: AMS Evaluator Tool

AMS Demonstration

The Analog Mixed Signal (AMS) technology leverages the digital signal processing
capabilities of Xilinx FPGA interconnect logic to enhance the performance and
functionality of the local XADC block. The AMS101 evaluation card offers a very limited
glimpse into the possibilities of the AMS concept by enabling efficient decimation.
Decimation
The AMS Evaluator tool enables decimation of the XADC data by a certain factor,
effectively trading off input bandwidth for higher SNR performance. This factor is defined
by the field shown on
decimation of 1 indicates that the XADC data is passed directly to the AMS Evaluator tool
without any filtering or decimation. The decimation function is carried out in the FPGA
using very little resources. The core building block is a decimate by 2 block. It first passes
the XADC data through a half-band filter and then decimates by a factor of 2, as shown in
Figure
X-Ref Target - Figure 4-8
X-Ref Target - Figure 4-8
Decimating by 2 cuts the input bandwidth in half. The frequency graph in the Frequency
Domain tab reflects this as the input bandwidth goes from 500 kHz with a decimation of 1
to 250 kHz with a decimation of 2.
To achieve a decimate by 4, the FPGA passes the XADC data through the decimate by 2
block and feeds back its output to the block's input so that it can be band-limited and
decimated by 2 again, giving an overall decimation rate of 4. For a decimation rate of 8, the
data is looped back through the decimate by 2 block a second time.
44
Figure 4-8. Select between a decimation rate of 1, 2, 4, 8, or 16. A
4-9.
Figure 4-8: Decimation Rate Selection
www.xilinx.com
Change
Decimation
between
1, 2, 4, 8, or 16
UG886_c4_08_062512
AMS101 Evaluation Card User Guide
UG886 (v1.3) November 6, 2013