Xilinx AMS101 User Manual page 39

In this mode, the data for V
press the Collect Data button. If you choose the simultaneous sampling option, then the
GUI changes to a dual display where XADC data for channel V
side by side as shown in
Display Options pull-down menu highlighted in
X-Ref Target - Figure 4-3
Clocking—XADC Sample Rate
The XADC is a dual 12-bit ADC running at speeds of up to 1 MSPS. The speed of the ADC
is dictated by the frequency of the clock, which is the divided-down version of the clock it
receives at the block level. The clock divider register of the XADC defines the division
factor. The GUI gives direct access to it (see
directly, or a desired ADC sample rate can be specified, and the GUI in this instance
calculates the most appropriate clock divider. By default, the clock divide register is set so
that the XADC sample rate is 1 MSPS. The XADC clock is 100 MHz and a clock divide ratio
of four gives a sample rate of 961.54 kSPS. See 7 Series FPGAs and Zynq-7000 All
Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide
(UG480)
AMS101 Evaluation Card User Guide
UG886 (v1.3) November 6, 2013
Figure
Display Options
Figure 4-3: Data Display for Simultaneous Sampling Mode
[Ref 6] for more details on the clocking of the XADC.
www.xilinx.com
/ V is captured, processed, and displayed every time you
P
N
4-3. To revert to the single channel data display, change the
Figure
When the Simul Sampled
option is selected, VAUX0 is
displayed on the left and
VAUX8 is displayed on the
right.
Figure 4-4). A clock divide ratio can be input
XADC Configuration
and V display
AUX0 AUX8
4-3.
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