Serdes Reference Clock; Serdes Channels - Lattice Semiconductor LFSC80E-P4-EV User Manual

Lattice Semiconductor
When Y3 or Y5 are enabled, the user should remove Y1 or Y4 respectively to eliminate contention issues between
the clock sources.
There are several resistor stuffing options that may be needed based on the user's requirements, R183 and R184
are left OPEN by factory default allowing connection to SMA inputs via R181 and R182. R181 and R182 are factory
populated with 0-ohm resistors. To utilize the Y1 or Y3 oscillators, the user should move the 0-ohms resistors from
R183 and R184 to R181 and R182.
This scenario is the same for R208 and R209 with R212 and R213 respectively.
A 100-ohm termination is optionally available and needs to be added to R185 and R186 if the SMA clock input are
not used. R185 and R186 are left OPEN at the factory and provide input termination to the B and A SERDES
Quads respectively.
Table 6. Reference Clock Input SMA Connections
A 100.0MHz surface-mounted oscillator (Y2) is also provided and fanned-out to three general-purpose FPGA
inputs.
SERDES
(see Appendix A, Figure 10)

SERDES Reference Clock

The 50-ohm terminated SMA connectors provide the supply reference clocks directly to the LatticeSC device. This
device will drive clocks to both SERDES quads via 100-ohm LVDS signaling. On-board clock oscillators mentioned
in the previous sections can be chosen to drive the same SERDES reference clocks.

SERDES Channels

Surface Mounted SMA Connections
(see Appendix A, Figure 10)
DC coupled top-mounted SMA connectors connect to the SERDES Tx and Rx channels of Quad B SERDES on
the left side (PCS 361). These pins are directly coupled to the designated SMA connector creating a path for both
input and output differential data.
Table 7. SERDES Connectors (see Appendix A, Figure 10)
LatticeSC PCI Express x4 Evaluation Board
J91 Reference + Input PCS361
J92 Reference - Input PCS361
J110 Reference + Input PCS360
J111 Reference - Input PCS360
J11 B_HDINN0_L
J6 B_HDINP0_L
J20 B_HDINN1_L
J16 B_HDINP1_L
J27 B_HDINN2_L
J23 B_HDINP2_L
J31 B_HDINN3_L
J28 B_HDINP3_L
J10 B_HDOUTN0_L
J5 B_HDOUTP0_L
9
User's Guide