Expansion Headers - Xilinx M401 User Manual

Detailed Description

10. Expansion Headers

The board contains expansion headers for easy expansion or adaptation of the board for
other applications. The expansion connectors use standard 0.1-inch headers. The
expansion connectors contain connections to single-ended and differential FPGA I/Os,
ground, 2.5V/3.3V/5V power, JTAG chain, and the IIC bus.
Differential Expansion I/O Connectors
Header J5 contains 16 pairs of differential signal connections to the FPGA I/Os. This
permits the signals on this connector to carry high-speed differential signals such as LVDS
data. All differential signals are routed with 100Ω differential trace impedance. Matched
length traces are used across all differential signals; consequently, these signals connect to
the FPGA I/O and can also be used as independent single-ended nets. The V
signals can be set to 2.5V or 3.3V by setting jumper J16.
connections on this expansion I/O connector.
Table 9: Expansion I/O Differential Connections (J5)
Header Pin Header Pin
(Diff Pair Pos) (Diff Pair Neg)
J5, Pin 4 J5, Pin 2
J5, Pin 8 J5, Pin 6
J5, Pin 12 J5, Pin 10
J5, Pin 16 J5, Pin 14
J5, Pin 20 J5, Pin 18
J5, Pin 24 J5, Pin 22
J5, Pin 28 J5, Pin 26
J5, Pin 32 J5, Pin 30
J5, Pin 36 J5, Pin 34
J5, Pin 40 J5, Pin 38
J5, Pin 44 J5, Pin 42
J5, Pin 48 J5, Pin 46
J5, Pin 52 J5, Pin 50
J5, Pin 56 J5, Pin 54
J5, Pin 60 J5, Pin 58
J5, Pin 64 J5, Pin 62
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20
Label Label
(Diff Pair Pos) (Diff Pair Neg)
HDR2_4 HDR2_2
HDR2_28 HDR2_26
HDR2_20 HDR2_18
HDR2_12 HDR2_10
HDR2_8 HDR2_6
HDR2_60 HDR2_58
HDR2_56 HDR2_54
HDR2_52 HDR2_50
HDR2_36 HDR2_34
HDR2_16 HDR2_14
HDR2_64 HDR2_62
HDR2_48 HDR2_46
HDR2_24 HDR2_22
HDR2_44 HDR2_42
HDR2_32 HDR2_30
HDR2_40 HDR2_38
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Table 9 summarizes the differential
FPGA Pin FPGA Pin
(Diff Pair Pos) (Diff Pair Neg)
AA18
Y19
Y20
W23
Y22
AA19
Y17
AB20
AE21
AE20
AD19
AC18
AF23
AF21
AF19
AF18
ML401/ML402/ML403 Evaluation Platform
UG080 (v2.5) May 24, 2006
R
of these
CCIO
Y18
W19
Y21
W24
Y23
AA20
AA17
AC20
AD21
AD20
AC19
AB18
AE23
AF22
AF20
AE18