User Pushbuttons (Active-High); Cpu Reset Button (Active-Low); Xgi Expansion Headers; Differential Expansion I/O Connectors - Xilinx ML50 Series User Manual

Chapter 1: ML501 Evaluation Platform

8. User Pushbuttons (Active-High)

Five active-High user pushbuttons are available for general purpose usage and are
arranged in a North-East-South-West-Center orientation (only the center one is cited in
Figure 1-2, page
Table 1-7: User Pushbutton Connections

9. CPU Reset Button (Active-Low)

The CPU reset button is an active-Low pushbutton and is used as a system or user reset
button. This pushbutton switch is wired only to an FPGA I/O pin so it can also be used as
a general-purpose pushbutton switch (see
Table 1-8: CPU Reset Connections

10. XGI Expansion Headers

The board contains expansion headers for easy expansion or adaptation of the board for
other applications. The expansion connectors use standard 0.1-inch headers. The
expansion connectors contain connections to single-ended and differential FPGA I/Os,
ground, 2.5V/3.3V/5V power, JTAG chain, and the IIC bus. All signals on connectors J4
and J6 have matched length traces that are matched to each other.

Differential Expansion I/O Connectors

Header J4 contains 16 pairs of differential signal connections to the FPGA I/Os. This
permits the signals on this connector to carry high-speed differential signals, such as LVDS
data. All differential signals are routed with 100Ω differential trace impedance. Matched
length traces are used across all differential signals on J4. Consequently, these signals
connect to the FPGA I/O, and they can be used as independent single-ended nets. The
V
summarizes the differential connections on this expansion I/O connector.
20
12). Table 1-7
Reference
Label/Definition
Designator
SW10
N (GPIO North)
SW12 E (GPIO East)
SW11 S (GPIO South)
SW13 W (GPIO West)
SW14 C (GPIO Center)
Reference
Label/Definition
Designator
SW3 CPU RESET
of these signals can be set to 2.5V or 3.3V by setting jumper J20.
CCIO
www.xilinx.com
summarizes the user pushbutton connections.
FPGA Pin
A22
A23
B22
C21
B21
Table 1-8).
FPGA Pin
T23
Table 1-9, page 21
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
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