Schematic Diagrams; Ez80 ® Development Platform; Figure 17. Ez80 ® Development Platform Schematic Diagram, #1 Of 5 - ZiLOG eZ80L92 User Manual

Schematic Diagrams

®
eZ80 Development Platform
Figures 17 through 21 diagram the layout of the eZ80
DO NOT USE J6_17 AND J6_35
J6
VCC
1 2
9V_DC
9VDC 3 4
ID_2
SCL 5 6
ID_1
SDA 7 8
GND ID_0
9 10
-DIS_MOD 11 12
GND
-MWAIT 13 14
EM_D0 15 16
-CS3
17 18
GND GND
19 20
EM_D7
21 22
EM_D6
23 24
EM_D5
25 26
EM_D4
27 28
EM_D3
29 30
EM_D2
31 32
EM_D1 33 34
35 36
GND GND
37 38
PB7_MOSI
PC7_RI1 39 40
PB6_MISO
PC6_DCD1 41 42
PB5_T5_O
PC5_DSR1 43 44
PB4_T4_O
PC4_DTR1 45 46
PB3_SCK
PC3_CTS1 47 48
PB2_SS
PC2_RTS1 49 50
PB1_T1_I
PC1_RXD1 51 52
PB0_T0_I
PC0_TXD1 53 54
55 56
57 58
59 60
GND
Header 30x2
J8
VDD
1 2
A0 A1
3 4
A2 A3
5 6
A4 A5
7 8
A6 A7
9 10
GND
11 12
A8 A9
13 14
A10 A11
15 16
A12 A13
17 18
A14 A15
19 20
GND
21 22
A16 A17
23 24
A18 A19
25 26
A20 A21
27 28
A22 A23
29 30
VDD
31 32
-RD
33 34
-RESET
35 36
-BUSACK 37 38
PHI
-NMI 39 40
GND GND
41 42
D0 D1
43 44
D2 D3
45 46
D4 D5
47 48
D6 D7
49 50
GND
51 52
-CS0 53 54
-CS2 55 56
-MEMRQ 57 58
GND
VDD
59 60
Header 30x2
VDD
U9A
3 2
3
TC74LVC08
VDD
U8A
GND
GND
R5 TDI
1K TDO
TC74LVT125 TCK
TVCC_RESETn
VDD
UM012906-0103
MA6
1 2
MA10
3 4
GND
5 6
MA8
7 8
MA13
9 10
MA15
11 12
MA18
ID_2 13 14
MA19
ID_1 15 16
MA2
ID_0 17 18
MA11
-DIS_CON 19 20
MA4
21 22
MA5
23 24
-DIS_ETH
-DIS_ETH 25 26
MA21
27 28
MA22
PD7_RI0
29 30
-M_CS0
PD6_DCD0
31 32
-M_CS2
PD5_DSR0
33 34
MD1
PD4_DTR0
35 36
MD3
PD3_CTS0
37 38
MD5
PD2_RTS0
39 40
MD7
PD1_RXD0 41 42
-M_MEMRQ
PD0_TXD0
43 44
GND
45 46
-M_WR
47 48
-BUSACK
49 50
Header 25x2
R1
10K
JP2
PB2_SS
PB7_MOSI
PB1_T1_I 1 2
PB5_T5_O
PB0_T0_I 3 4
VDD PB3_SCK
5 6
PB1_T1_I
7 8
GND
9 10
PC6_DCD1
11 12
PC4_DTR1
13 14
PC2_RTS1
15 16
PC0_TXD1
17 18
PD6_DCD0
19 20
GND PD5_DSR0
21 22
PD3_CTS0
23 24
PD1_RXD0
25 26
TDO
27 28
GND
29 30
GND TCK
31 32
RTC_VDD
VDD
33 34
SCL
35 36
SDA
37 38
-FLASHWE
R3
39 40
GND 10K -M_CS3
41 42
-RESET
43 44
VDD
45 46
HALT_SLP
47 48
VDD
49 50
VDD
Header 25x2
-WR
INSTRD
VDD
-BUSREQ
PHI
ZDI
GND
INTERFACE
J4
-CS1
VDD PRSTn
-CS_EX 1 2
-IORQ 3 4
GND
5 6
Header 3x2
VDD
R4
10K
1
-RESET
2
RX D2
1
P1
1 2
3 4
GND
5 6
D4
TX
7 8
TMS 1
9 10
PRSTn
11 12
TRIGOUT
13 14
con 7x2
®
Figure 17. eZ80 Development Platform Schematic Diagram, #1 of 5
®
Development Platform.
MA0 U1
MA3
VDD MA0 2 18
A1 Y1
MA7 MA1
4 16
A2 Y2
MA9 MA2
6 14
A3 Y3
MA14 MA3
8 12
A4 Y4
MA16 MA4
11 9
A5 Y5
GND MA5
13 7
A6 Y6
MA1 MA6
15 5
A7 Y7
MA12 MA7
17 3
A8 Y8
MA20
MA17 VDD
1 20
1OE VCC
-DIS_FL GND
19 10
-DIS_FL 2OE GND
VDD
MA23
-M_CS1
74LVC244A
MD0 U3
MD2
MD4 MA8
2 18
A1 Y1
GND MA9
4 16
A2 Y2
MD6 MA10
6 14
A3 Y3
-M_IORQ MA11
8 12
A4 Y4
-M_RD MA12 11 9
A5 Y5
INSTRD MA13
13 7
A6 Y6
-BUSREQ MA14
15 5
A7 Y7
MA15
17 3
A8 Y8
VDD
R2 1 20
1OE VCC
10K GND
19 10
2OE GND
PB6_MISO
PB4_T4_O
PB2_SS VDD
74LVC244A
PB0_T0_I
PC7_RI1 U5
PC5_DSR1
PC3_CTS1 MA16
2 18
A1 Y1
PC1_RXD1 MA17
4 16
A2 Y2
PD7_RI0 MA18
6 14
A3 Y3
GND MA19
8 12
A4 Y4
PD4_DTR0 MA20
11 9
A5 Y5
PD2_RTS0 MA21
13 7
A6 Y6
MA22
PD0_TXD0
15 5
A7 Y7
TDI MA23 17 3
A8 Y8
TRIGOUT
TMS VDD
1 20
1OE VCC
M_PHI GND GND
19 10
2OE GND
GND
74LVC244A
-DIS_IRDA
-MWAIT
GND
J5 J1
-NMI
M_TIP
1
M_TIP
M_RING
2
M_RING
R19
HEADER 2
10K
TCK
TDI
J9
-MRESET
1
-MRESET
2
DCD
R8
GND
D1 3
0
1 2 4
5
R9
6
2 0 7
8
R20
D3 DTR 9
1 2 0
R21
HEADER 9
2 0 HEADER 32
MODEM CONNECTORS
PRELIMINARY
A[23:0]
A[23:0]
A0
A1
A2
A3 SCL
A4
A5
A6
J2
A7
1
-DIS_IRDA
GND
2
C30
0.1uF
HEADER 2
J7
A8
A9 -FLASHWE
1
A10 GND
2
A11
A12
A13
HEADER 2
A14 -M_CS0
A15 -M_CS1
-M_CS2
-M_IORQ
-M_MEMRQ
-M_WR
C31
0.1uF -M_RD
-M_CS3
M_PHI
A16
A17 GND
A18
A19
A20
A21
A22
A23
J12
VCC
C33
1
0.1uF
2
VDD
3
Header 3
MODEM's
1
AGND
2
-DIS_MOD
3 U7
VCC
4
MD0
5 2
A0
MD1
6 3
A1
MD2
7 4
A2
MD3
8 5
A3
MD4
9 6
A4
10 MD5 7
A5
MD6
11 8
A6
MD7
12 9
A7
13
-M_RD
14 1
DIR VCC
15 19
-L_RD OE GND
16
17
18 74LVC245/SO
19
20
21
22
VCC
23
VCC
GND
24
PC4_DTR1 VDD
25
VDD
PC6_DCD1 GND
26
GND
PC3_CTS1
27
PC5_DSR1
28
PC7_RI1
29
30 PC0_TXD1
PC1_RXD1
31
PC2_RTS1
32
eZ80L92 Development Kit
User Manual
U2
1 5 SDA
A0 SDA
GND
2
A1
VDD
8
VCC
6
SCL
4
GND
7 3
WP NC
AT24C128
GND
U21
2 23
A1 Y1 -CS0
3 22
A2 Y2 -CS1
4 21
A3 Y3 -CS2
5 20
A4 Y4 -IORQ
6 19
A5 Y5 -MEMRQ
7 18
A6 Y6 -WR
8 17
A7 Y7 -RD
9 16
A8 Y8 -CS3
10 15
A9 Y9 PHI
11 14
A10 Y10
VDD
1 24
OE1 VCC
GND
13 12
OE2 GND
C34
74LVC827/SO 0.1uF
D[7:0]
D[7:0]
D0
18
B0
D1
17
B1
D2
16
B2
D3
15
B3
D4
14
B4
13 D5
B5
D6
12
B6
D7
11
B7
VDD
20
10
C1
0.1uF
GND
MD[7:0]
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
Schematic Diagrams
63