Ez80L92 Module; Figure 22. Ez80L92 Module Schematic Diagram, #1 Of 9-Top Level - ZiLOG eZ80L92 User Manual

eZ80L92 Module

Figures 22 through 30 diagram the layout of the eZ80L92 Module.
03
RAM
SRAM
D[0..7]
D[0..7]
A[0..23]
A[0..23]
-RD
-RD
-WR
-WR
-CS1
-CS1
04
ROM
NOR-Flash
D[0..7]
D[0..7]
A[0..23]
A[0..23]
-RD
-RD
-WR
-WR
-CSFLASH
-CSFLASH
-RESFLASH
-RESFLASH
-FLASHWE
-FLASHWE
09
Power
PowerSupply
V3.3
V3.3
GND
GND
UM012906-0103
02
CPU
eZ80
D[0..7] -RESET
A[0..23]
-IOREQ
-RD -IOREQ
-MREQ
-WR -MREQ
-INSTRD
-INSTRD
-WAIT
-WAIT
-HALT_SLP
-HALT_SLP
-BUSREQ
-BUSREQ
-BUSACK
-BUSACK
-NMI
-NMI
CLK_OUT
CLK_OUT
RTC_VDD
RTC_VDD
IICSDA
IICSDA
IICSCL
IICSCL
PB[0..7]
PB[0..7]
PC[0..7]
PC[0..7]
PD[0..7]
PD[0..7]
-CS[0..3]
-CS[0..3]
JTAG[1..4]
JTAG[1..4]
TDO
TDO
05
Ethernet
CS8900A
SD[0..7]
SA[0..3]
IOCHRDY
-ETHRD
-ETHWR
ETHIRQ
ETHIRQ
-SLEEP
-SLEEP
-ACTIVE
-ACTIVE
-DIS_ETH
Figure 22. eZ80L92 Module Schematic Diagram, #1 of 9—Top Level
PRELIMINARY
07
Peripherals
Reset
IRDA_TXD
IRDA_TXD
-RESET IRDA_RXD
-RESET IRDA_RXD
IRDA_SD
IRDA_SD
06
Logic
CTRL-Logic
-RESET
-RESET
-WAIT
-WAIT
IRDA_TXD
IRDA_RXD
IRDA_SD
-DIS_FL
PD[0..7]
-DIS_IRDA
-CS[0..3]
-CSFLASH
-RESFLASH
SD[0..7]
SA[0..3]
IOCHRDY
-ETHRD
-ETHWR
eZ80L92 Development Kit
User Manual
08
Connector
Headers
-RESET
-RESET
-FLASHWE
-FLASHWE
-IOREQ
-IOREQ
-MREQ
-MREQ
-INSTRD
-INSTRD
-WAIT
-WAIT
-HALT_SLP
-HALT_SLP
-BUSREQ
-BUSREQ
-BUSACK
-BUSACK
-NMI
-NMI
CLK_OUT
CLK_OUT
RTC_VDD
RTC_VDD
IICSDA
IICSDA
IICSCL
IICSCL
D[0..7]
D[0..7]
A[0..23]
A[0..23]
IRDA_TXD
IRDA_RXD -WR
-WR
IRDA_SD -RD
-RD
-DIS_FL
-DIS_FL
-DIS_IRDA
-DIS_IRDA
PB[0..7]
PB[0..7]
-CSFLASH PC[0..7]
PC[0..7]
PD[0..7]
PD[0..7]
-RESFLASH
-CS[0..3]
-CS[0..3]
JTAG[1..4]
JTAG[1..4]
TDO
TDO
-DIS_ETH
V3.3
V3.3_EXT
GND
GND_EXT
Schematic Diagrams
68