ZiLOG eZ80L92 User Manual page 25

Peripheral Bus Connector Identification—JP1
Pin # Symbol
46 RD
47 WR
48 INSTRD
49 BUSACK
50 BUSREQ
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80L92 Module Schematics
through 66.
2. The Power and Ground nets are connected directly to the eZ80L92 device.
Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be
below 10pF to satisfy the timing requirements for the eZ80
pulled to either V or GND, depending on their inactive levels to reduce power consumption and
DD
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91's Peripheral Power-Down Register.
UM012906-0103
®
Table 2. eZ80 Development Platform
Signal Direction
Bidirectional
Bidirectional
Input
Input
Output
PRELIMINARY
eZ80L92 Development Kit
1
(Continued)
Active Level
Low
Low
Low
Pull-Up 10KΩ; Low
Pull-Up 10KΩ; Low
®
CPU. All unused inputs should be
User Manual
2
eZ80L92 Signal
Yes
Yes
Yes
Yes
Yes
on pages 64
Operational Description
15