D[0..7]
D[0..7]
A[0..23]
A[0..23]
PD[0..7]
PD[0..7]
-RESET
-RESET
-WAIT
-WAIT
-DIS_FL
-DIS_FL
-DIS_IRDA
-DIS_IRDA
-RD
-RD
-WR
-WR
-CS[0..3]
-CS[0..3]
R30
10k
0603
-DIS_FL
R17
10k
0603
-DIS_IRDA
UM012906-0103
D[0..7]
A[0..23]
only A0,A1,A2,A3
are used here
PD3 and PD5
not used here
-RD
-CS3
=
-CSETH
-WR
-CS1 and-CS2
not used
here
VDD
U2B
DIS_FL
3
4
-CS0
74LVC04/SO
U2C
DIS_IRDA
5
6
PD2
IR_SD
=
74LVC04/SO
Figure 30. eZ80L92 Module Schematic Diagram, #9 of 9—Control Logic
=
SD[0..7]
SA[0..3]
A0
=
SA0
A1
=
SA1
A2
=
SA2
A3
=
SA3
VDD
U6D
12
-ETHRD
11
13
74LCX32
TSSOP14
U6A
1
-ETHWR
3
2
74LCX32
TSSOP14
U6B
4
-CSFLASH
6
5
74LCX32
TSSOP14
U6C
9
IRDA_SD
8
10
74LCX32
TSSOP14
VDD
VSS
PRELIMINARY
eZ80L92 Development Kit
SD[0..7]
SA[0..3]
-ETHRD
-ETHWR
PD4
=
ETHIRQ
R14
0R
PD7
-SLEEP
R15
0R
PD6
-ACTIVE
don't stuff
R35
0
-WAIT
PD0
=
IRDA_TXD
PD1
=
IRDA_RXD
IRDA_SD
-RESET
=
-RESFLASH
-CSFLASH
V3.3
GND
User Manual
76
SD[0..7]
SA[0..3]
-ETHRD
-ETHWR
ETHIRQ
-SLEEP
-ACTIVE
IOCHRDY
IRDA_TXD
IRDA_RXD
IRDA_SD
-RESFLASH
-CSFLASH
Schematic Diagrams
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