ZiLOG eZ80L92 User Manual page 42

eZ80L92 Development Kit
User Manual
32
Note:
Operational Description
address decoder, implemented in the Generic Array Logic device,
GAL22LV10D (U10).
Flash Memory
The eZ80L92 Development Kit allows Flash memories between 1MB
and 4MB. The chips are housed in wide TSOP40 cases. Flash ROM
access times are 55–150ns; typically 90ns.
When accessing Flash memory, the eZ80L92 device should be configured
to operate in Intel bus mode to satisfy setup and hold times and to prevent
bus contention with a Write cycle that could possibly follow. For proper
CPU operation at 48MHz, first set the bus mode control register
CS0_BMC (I/O address
register CS0_CTL (I/O address
Bus Mode with two system clocks per bus cycle and zero wait states.
Memory Map
A memory map of the eZ80
ory and SRAM on the eZ80L92 Module are addressed when CS0 and CS1
are active Low. SRAM on the eZ80
when CS2 is active Low.
The Ethernet controller, located on the eZ80L92 Module, is mapped as an
I/O device at address
) to , then set the Chip Select Control
F0h 82h
) to
AAh 08h
®
CPU is illustrated in Figure 10. Flash mem-
®
Development Platform is addressed
. It uses CS3.
300h
PRELIMINARY
. These settings select Intel
UM012906-0103