Table 2. Ez80 ® Development Platform Peripheral Bus Connector Identification-Jp11 - ZiLOG eZ80L92 User Manual

eZ80L92 Development Kit
User Manual
12
Pin # Symbol
1 A6
2 A0
3 A10
4 A3
5 GND
6 V
DD
7 A8
8 A7
9 A13
10 A9
11 A15
12 A14
13 A18
14 A16
15 A19
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80L92 Module Schematics
through 66.
2. The Power and Ground nets are connected directly to the eZ80L92 device.
Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be
below 10pF to satisfy the timing requirements for the eZ80
pulled to either V
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F91's Peripheral Power-Down Register.
Operational Description
Table 2. eZ80
Peripheral Bus Connector Identification—JP1
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
or GND, depending on their inactive levels to reduce power consumption and
DD
®
Development Platform
Active Level
®
CPU. All unused inputs should be
PRELIMINARY
1
2
eZ80L92 Signal
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
on pages 64
UM012906-0103