Nand Flash; Secure Digital Card Interface; Serial Eeprom; Daughter Board Interface - GE MAC 5000 Service Manual

NAND Flash

Secure Digital Card Interface

Serial EEPROM

Daughter Board Interface

2-26
Equipment Overview: Theory of Operation
There are two 32 Mbytes NAND Flash in -006 board. One is used for
storing FPGA configuration data and system software. The other is for
data storage. The access to NAND flash is through a dedicated smart
media interface logic provided by ATMEL CPU. Unlike -005 board
NAND flash chips are accessed through the buffer U53 instead of Xbus.
The NAND Flash control signals are changed to GPIO mode while
configuring FPGA in fly by fashion. Wear-leveling algorithm is
implemented for the data storage NAND flash to extend the life.
The SD card interface is provided to support software update and
external data storage application. The external storage application using
SD card is not enabled in the MAC 5000 with the -006 CPU board.
The socket provides card detection and write protect status signal.
ATMEL CPU has built in secure digital card interface controller. But
there is a bug in the current revision of the ATMEL CPU, which swaps
bits within the transmitted / received nibbles. Since the software
overhead to correct this is high, SD card interface support only SPI mode.
However all the SD card interface signals are terminated at the
connector through a set of resistors, which are not placed, so that we can
go for the true SD card interface in future.
System setup information, option enables and other machine specific
data is stored in 32 KByte serial EEPROM. The SPI interface to the
EEPROM is provided by the FPGA.
The interface is realized using a 100 pin high speed connector. The
interface will be active only in the MAC 5500. This interface provide two
serial interfaces, PC Card interface signals, USB host and various power
supply tappings. The PC Card interface and USB interface are no longer
in the requirement list. All the PC Card signals are buffered. The buffer
will be active only when a valid PC card is inserted in the daughter
board. Out of the two serial interfaces, one provides full hardware
handshaking. This is derived from the Super IO COM2. The COM2 can
be routed to either COM2 external connector or to the daughter board
interface using a multiplexer controlled using ATMEL CPU port pins.
The second serial interface has limited hardware control and derived
from ATMEL CPU UART 1.
MAC™ 5000 resting ECG analysis system
2024917-010
Revision B